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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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--
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--
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-- Author: Christoph Zimmermann
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-- Author: Christoph Zimmermann
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-- Date of creation: 17. December 2009
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-- Date of creation: 17. December 2009
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-- Description:
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-- Description:
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-- This is a wrapper for a FIFO that was generated with the Xilinx Coregenerator
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-- This is a wrapper for a FIFO that was generated with the Xilinx
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-- to hide the vendor specific stuff and match our naming conventions.
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-- Coregenerator to hide the vendor specific stuff and match our naming
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-- conventions.
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--
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--
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-- Target Devices: Xilinx FPGA's due to use of Coregenerator IP cores
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-- Target Devices: Xilinx FPGA's due to use of Coregenerator IP cores
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-- Tool versions: 11.1
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-- Tool versions: 11.1
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-- Dependencies:
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-- Dependencies:
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--
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--
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library work;
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library work;
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use work.GECKO3COM_defines.all;
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use work.GECKO3COM_defines.all;
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entity receive_fifo is
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entity receive_fifo is
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generic (
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generic (
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BUSWIDTH : integer := 16); -- vector size of the FIFO databusses
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BUSWIDTH : integer := 32); -- vector size of the FIFO databusses
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port (
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port (
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i_din : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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i_din : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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i_clk : in std_logic;
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i_clk : in std_logic;
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i_rd_en : in std_logic;
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i_rd_en : in std_logic;
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i_rst : in std_logic;
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i_rst : in std_logic;
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rd_clk : in std_logic;
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rd_clk : in std_logic;
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rd_en : in std_logic;
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rd_en : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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wr_clk : in std_logic;
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wr_clk : in std_logic;
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wr_en : in std_logic;
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wr_en : in std_logic;
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dout : out std_logic_vector(BUSWIDTH-1 downto 0);
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dout : out std_logic_vector(31 downto 0);
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empty : out std_logic;
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empty : out std_logic;
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full : out std_logic);
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full : out std_logic);
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end component;
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end component;
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-- Synplicity black box declaration
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-- Synplicity black box declaration
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