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#ChipScope Core Inserter Project File Version 3.0
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#ChipScope Core Inserter Project File Version 3.0
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#Tue Jan 26 16:27:50 CET 2010
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#Wed Jan 27 15:45:20 CET 2010
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Project.device.designInputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/gpif_com_test_cs.ngc
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Project.device.designInputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/gpif_com_test_cs.ngc
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Project.device.designOutputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/gpif_com_test_cs.ngc
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Project.device.designOutputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/gpif_com_test_cs.ngc
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Project.device.deviceFamily=6
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Project.device.deviceFamily=6
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Project.device.enableRPMs=true
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Project.device.enableRPMs=true
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Project.device.outputDirectory=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/_ngo
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Project.device.outputDirectory=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/_ngo
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Line 16... |
Project.icon.triggerOutPinName=
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Project.icon.triggerOutPinName=
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Project.unit.dimension=1
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Project.unit.dimension=1
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Project.unit<0>.clockChannel=i_IFCLK_BUFGP
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Project.unit<0>.clockChannel=i_IFCLK_BUFGP
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Project.unit<0>.clockEdge=Rising
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Project.unit<0>.clockEdge=Rising
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Project.unit<0>.dataChannel<0>=o_WRX_OBUF
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Project.unit<0>.dataChannel<0>=o_WRX_OBUF
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Project.unit<0>.dataChannel<10>=GPIF_INTERFACE s_dbus_out<8>
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Project.unit<0>.dataChannel<10>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd9
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Project.unit<0>.dataChannel<11>=GPIF_INTERFACE s_dbus_out<9>
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Project.unit<0>.dataChannel<11>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd10
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Project.unit<0>.dataChannel<12>=GPIF_INTERFACE s_dbus_out<10>
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Project.unit<0>.dataChannel<12>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd11
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Project.unit<0>.dataChannel<13>=GPIF_INTERFACE s_dbus_out<11>
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Project.unit<0>.dataChannel<13>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd12
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Project.unit<0>.dataChannel<14>=GPIF_INTERFACE s_dbus_out<12>
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Project.unit<0>.dataChannel<14>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd13
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Project.unit<0>.dataChannel<15>=GPIF_INTERFACE s_dbus_out<13>
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Project.unit<0>.dataChannel<15>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd14
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Project.unit<0>.dataChannel<16>=GPIF_INTERFACE s_dbus_out<14>
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Project.unit<0>.dataChannel<16>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd15
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Project.unit<0>.dataChannel<17>=GPIF_INTERFACE s_dbus_out<15>
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Project.unit<0>.dataChannel<17>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd16
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Project.unit<0>.dataChannel<18>=GPIF_INTERFACE s_dbus_trans_dir
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Project.unit<0>.dataChannel<18>=GPIF_INTERFACE s_dbus_trans_dir
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Project.unit<0>.dataChannel<19>=GPIF_INTERFACE o_RX
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Project.unit<0>.dataChannel<19>=GPIF_INTERFACE o_RX
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Project.unit<0>.dataChannel<1>=i_RDYU_IBUF
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Project.unit<0>.dataChannel<1>=i_RDYU_IBUF
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Project.unit<0>.dataChannel<20>=GPIF_INTERFACE o_TX
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Project.unit<0>.dataChannel<20>=GPIF_INTERFACE o_TX
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Project.unit<0>.dataChannel<21>=GPIF_INTERFACE s_U2X_AM_FULL
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Project.unit<0>.dataChannel<21>=GPIF_INTERFACE s_U2X_AM_FULL
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Line 37... |
Project.unit<0>.dataChannel<25>=s_RX_DATA<0>
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Project.unit<0>.dataChannel<25>=s_RX_DATA<0>
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Project.unit<0>.dataChannel<26>=s_RX_DATA<1>
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Project.unit<0>.dataChannel<26>=s_RX_DATA<1>
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Project.unit<0>.dataChannel<27>=s_RX_DATA<2>
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Project.unit<0>.dataChannel<27>=s_RX_DATA<2>
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Project.unit<0>.dataChannel<28>=s_RX_DATA<3>
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Project.unit<0>.dataChannel<28>=s_RX_DATA<3>
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Project.unit<0>.dataChannel<29>=s_RX_DATA<4>
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Project.unit<0>.dataChannel<29>=s_RX_DATA<4>
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Project.unit<0>.dataChannel<2>=GPIF_INTERFACE s_dbus_out<0>
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Project.unit<0>.dataChannel<2>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd1
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Project.unit<0>.dataChannel<30>=s_RX_DATA<5>
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Project.unit<0>.dataChannel<30>=s_RX_DATA<5>
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Project.unit<0>.dataChannel<31>=s_RX_DATA<6>
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Project.unit<0>.dataChannel<31>=s_RX_DATA<6>
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Project.unit<0>.dataChannel<32>=s_RX_DATA<7>
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Project.unit<0>.dataChannel<32>=s_RX_DATA<7>
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Project.unit<0>.dataChannel<33>=s_RX_DATA<8>
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Project.unit<0>.dataChannel<33>=s_RX_DATA<8>
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Project.unit<0>.dataChannel<34>=s_RX_DATA<9>
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Project.unit<0>.dataChannel<34>=s_RX_DATA<9>
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Project.unit<0>.dataChannel<35>=s_RX_DATA<10>
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Project.unit<0>.dataChannel<35>=s_RX_DATA<10>
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Project.unit<0>.dataChannel<36>=s_RX_DATA<11>
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Project.unit<0>.dataChannel<36>=s_RX_DATA<11>
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Project.unit<0>.dataChannel<37>=s_RX_DATA<12>
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Project.unit<0>.dataChannel<37>=s_RX_DATA<12>
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Project.unit<0>.dataChannel<38>=s_RX_DATA<13>
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Project.unit<0>.dataChannel<38>=s_RX_DATA<13>
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Project.unit<0>.dataChannel<39>=s_RX_DATA<14>
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Project.unit<0>.dataChannel<39>=s_RX_DATA<14>
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Project.unit<0>.dataChannel<3>=GPIF_INTERFACE s_dbus_out<1>
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Project.unit<0>.dataChannel<3>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd2
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Project.unit<0>.dataChannel<40>=s_RX_DATA<15>
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Project.unit<0>.dataChannel<40>=s_RX_DATA<15>
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Project.unit<0>.dataChannel<41>=s_EMPTY
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Project.unit<0>.dataChannel<41>=s_EMPTY
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Project.unit<0>.dataChannel<42>=i_WRU_IBUF
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Project.unit<0>.dataChannel<42>=i_WRU_IBUF
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Project.unit<0>.dataChannel<43>=GPIF_INTERFACE s_X2U_RD_EN
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Project.unit<0>.dataChannel<43>=GPIF_INTERFACE s_X2U_RD_EN
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Project.unit<0>.dataChannel<44>=s_RD_EN
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Project.unit<0>.dataChannel<44>=s_RD_EN
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Project.unit<0>.dataChannel<45>=GPIF_INTERFACE i_EOM
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Project.unit<0>.dataChannel<45>=GPIF_INTERFACE i_EOM
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Project.unit<0>.dataChannel<46>=GPIF_INTERFACE s_X2U_FULL_IFCLK
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Project.unit<0>.dataChannel<46>=GPIF_INTERFACE s_X2U_FULL_IFCLK
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Project.unit<0>.dataChannel<4>=GPIF_INTERFACE s_dbus_out<2>
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Project.unit<0>.dataChannel<47>=
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Project.unit<0>.dataChannel<5>=GPIF_INTERFACE s_dbus_out<3>
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Project.unit<0>.dataChannel<4>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd3
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Project.unit<0>.dataChannel<6>=GPIF_INTERFACE s_dbus_out<4>
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Project.unit<0>.dataChannel<5>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd4
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Project.unit<0>.dataChannel<7>=GPIF_INTERFACE s_dbus_out<5>
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Project.unit<0>.dataChannel<6>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd5
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Project.unit<0>.dataChannel<8>=GPIF_INTERFACE s_dbus_out<6>
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Project.unit<0>.dataChannel<7>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd6
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Project.unit<0>.dataChannel<9>=GPIF_INTERFACE s_dbus_out<7>
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Project.unit<0>.dataChannel<8>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd7
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Project.unit<0>.dataChannel<9>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd8
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Project.unit<0>.dataDepth=512
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Project.unit<0>.dataDepth=512
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Project.unit<0>.dataEqualsTrigger=false
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Project.unit<0>.dataEqualsTrigger=false
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Project.unit<0>.dataPortWidth=47
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Project.unit<0>.dataPortWidth=47
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Project.unit<0>.enableGaps=false
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Project.unit<0>.enableGaps=false
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Project.unit<0>.enableStorageQualification=true
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Project.unit<0>.enableStorageQualification=true
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