| Line 1... |
Line 1... |
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
|
|
library work;
|
library work;
|
use work.USB_TMC_func.all;
|
|
use work.USB_TMC_IP_Defs.all;
|
use work.USB_TMC_IP_Defs.all;
|
use work.USB_TMC_cmp.all;
|
use work.USB_TMC_cmp.all;
|
|
|
|
|
entity USB_TMC_IP is
|
entity USB_TMC_IP is
|
| Line 40... |
Line 39... |
-- interconection signals
|
-- interconection signals
|
|
|
signal s_FIFOrst : std_logic;
|
signal s_FIFOrst : std_logic;
|
|
|
-- U2X
|
-- U2X
|
signal s_U2X_FIFO_WR_EN,
|
signal s_U2X_WR_EN,
|
s_U2X_FIFO_RD_EN,
|
s_U2X_RD_EN,
|
s_U2X_FULL,
|
s_U2X_FULL,
|
s_U2X_AM_FULL,
|
s_U2X_AM_FULL,
|
s_U2X_EMPTY,
|
s_U2X_EMPTY,
|
s_U2X_AM_EMPTY : std_logic;
|
s_U2X_AM_EMPTY : std_logic;
|
|
|
-- X2U
|
-- X2U
|
signal s_X2U_FIFO_WR_EN,
|
signal s_X2U_WR_EN,
|
s_X2U_FIFO_RD_EN,
|
s_X2U_RD_EN,
|
s_X2U_FULL,
|
s_X2U_FULL,
|
s_X2U_AM_FULL,
|
s_X2U_AM_FULL,
|
s_X2U_EMPTY,
|
s_X2U_EMPTY,
|
s_X2U_AM_EMPTY : std_logic;
|
s_X2U_AM_EMPTY : std_logic;
|
|
|
-- data signals
|
|
signal s_X2U_FIFO_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- data bus
|
-- data bus
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
-- data signals
|
-- data signals
|
| Line 70... |
Line 65... |
signal s_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
|
signal s_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
|
|
|
signal s_opb_in : std_logic_vector(SIZE_DBUS_FPGA-1 downto 0);
|
signal s_opb_in : std_logic_vector(SIZE_DBUS_FPGA-1 downto 0);
|
signal s_opb_out : std_logic_vector(SIZE_DBUS_FPGA-1 downto 0);
|
signal s_opb_out : std_logic_vector(SIZE_DBUS_FPGA-1 downto 0);
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- USBTMC
|
|
-------------------------------------------------------------------------------
|
|
|
|
type tHeaderRegAccess is (EOT,SET);
|
|
|
|
signal s_U2X_HeaderReg,
|
|
s_X2U_HeaderReg : tHeaderReg;
|
|
|
|
signal s_U2X_setHeader,
|
|
s_X2U_setHeader : tHeaderRegAccess;
|
|
|
|
|
|
signal s_U2X_extracted : std_logic;
|
|
|
|
-- header extraction
|
|
signal s_U2X_WR_EN,
|
|
-- s_X2U_WR_EN,
|
|
-- s_U2X_RD_EN,
|
|
s_X2U_RD_EN : std_logic;
|
|
|
|
|
|
|
|
-- -------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------
|
-- -- UART
|
-- -- UART
|
-- -------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------
|
-- signal s_UART_RD : std_logic;
|
-- signal s_UART_RD : std_logic;
|
-- signal s_UART_WR : std_logic;
|
-- signal s_UART_WR : std_logic;
|
| Line 135... |
Line 106... |
|
|
F_IN : fifo_U2X_2C_1024B
|
F_IN : fifo_U2X_2C_1024B
|
port map (
|
port map (
|
din => s_dbus_in,
|
din => s_dbus_in,
|
rd_clk => i_SYSCLK,
|
rd_clk => i_SYSCLK,
|
rd_en => s_U2X_FIFO_RD_EN,
|
rd_en => s_U2X_RD_EN,
|
rst => s_FIFOrst,
|
rst => s_FIFOrst,
|
wr_clk => i_IFCLK ,
|
wr_clk => i_IFCLK ,
|
wr_en => s_U2X_FIFO_WR_EN,
|
wr_en => s_U2X_WR_EN,
|
almost_empty => s_U2X_AM_EMPTY,
|
almost_empty => s_U2X_AM_EMPTY,
|
almost_full => s_U2X_AM_FULL,
|
almost_full => s_U2X_AM_FULL,
|
dout => s_opb_in,
|
dout => s_opb_in,
|
empty => s_U2X_EMPTY,
|
empty => s_U2X_EMPTY,
|
full => s_U2X_FULL
|
full => s_U2X_FULL
|
| Line 151... |
Line 122... |
|
|
F_OUT : fifo_X2U_2C_1024B
|
F_OUT : fifo_X2U_2C_1024B
|
port map (
|
port map (
|
din => s_opb_out,
|
din => s_opb_out,
|
rd_clk => i_IFCLK,
|
rd_clk => i_IFCLK,
|
rd_en => s_X2U_FIFO_RD_EN,
|
rd_en => s_X2U_RD_EN,
|
rst => s_FIFOrst,
|
rst => s_FIFOrst,
|
wr_clk => i_SYSCLK,
|
wr_clk => i_SYSCLK,
|
wr_en => s_X2U_FIFO_WR_EN,
|
wr_en => s_X2U_WR_EN,
|
almost_empty => s_X2U_AM_EMPTY,
|
almost_empty => s_X2U_AM_EMPTY,
|
almost_full => s_X2U_AM_FULL,
|
almost_full => s_X2U_AM_FULL,
|
dout => s_X2U_FIFO_dbus_out,
|
dout => s_dbus_out,
|
empty => s_X2U_EMPTY,
|
empty => s_X2U_EMPTY,
|
full => s_X2U_FULL
|
full => s_X2U_FULL
|
);
|
);
|
|
|
|
|
FSM_GPIF : gpif_com
|
FSM_GPIF : gpif_com
|
port map (
|
port map (
|
i_nReset => i_nReset,
|
i_nReset => i_nReset,
|
i_IFCLK => i_IFCLK,
|
i_IFCLK => i_IFCLK,
|
i_WRU => i_WRU,
|
i_WRU => i_WRU,
|
i_RDYU => i_RDYU,
|
i_RDYU => i_RDYU,
|
i_U2X_FULL => s_U2X_FULL,
|
i_U2X_FULL => s_U2X_FULL,
|
i_U2X_AM_FULL => s_U2X_AM_FULL,
|
i_U2X_AM_FULL => s_U2X_AM_FULL,
|
i_X2U_AM_EMPTY => s_X2U_AM_EMPTY,
|
i_X2U_AM_EMPTY => s_X2U_AM_EMPTY,
|
i_X2U_EMPTY => s_X2U_EMPTY,
|
i_X2U_EMPTY => s_X2U_EMPTY,
|
i_dbus => s_dbus_out, -- data from the FPGA usr dep application
|
i_dbus => s_dbus_out,
|
o_U2X_WR_EN => s_U2X_WR_EN, -- wr ena for in fifo
|
o_U2X_WR_EN => s_U2X_WR_EN,
|
o_X2U_RD_EN => s_X2U_RD_EN, -- rd ena for out fifo
|
o_X2U_RD_EN => s_X2U_RD_EN,
|
o_FIFOrst => s_FIFOrst, -- abord dedection to rst the fifo's
|
o_FIFOrst => s_FIFOrst,
|
o_WRX => o_WRX,
|
o_WRX => o_WRX,
|
o_RDYX => o_RDYX,
|
o_RDYX => o_RDYX,
|
o_LEDrx => o_LEDrx,
|
o_LEDrx => o_LEDrx,
|
o_LEDtx => o_LEDtx,
|
o_LEDtx => o_LEDtx,
|
o_LEDrun => o_LEDrun,
|
o_LEDrun => o_LEDrun,
|
o_dbus => s_dbus_in, -- data from the GPIF
|
o_dbus => s_dbus_in,
|
b_dbus => b_dbus
|
b_dbus => b_dbus
|
);
|
);
|
|
|
|
|
Loopback : USB_TMC_IP_loopback
|
Loopback : USB_TMC_IP_loopback
|
| Line 195... |
Line 167... |
i_U2X_EMPTY => s_U2X_EMPTY,
|
i_U2X_EMPTY => s_U2X_EMPTY,
|
i_U2X_AM_EMPTY => s_U2X_AM_EMPTY,
|
i_U2X_AM_EMPTY => s_U2X_AM_EMPTY,
|
i_X2U_AM_FULL => s_X2U_AM_FULL,
|
i_X2U_AM_FULL => s_X2U_AM_FULL,
|
i_X2U_FULL => s_X2U_FULL,
|
i_X2U_FULL => s_X2U_FULL,
|
i_U2X_DATA => s_opb_in,
|
i_U2X_DATA => s_opb_in,
|
o_X2U_DATA => s_opb_out,
|
o_U2X_RD_EN => s_U2X_RD_EN,
|
o_U2X_RD_EN => s_U2X_FIFO_RD_EN,
|
o_X2U_WR_EN => s_X2U_WR_EN,
|
o_X2U_WR_EN => s_X2U_FIFO_WR_EN
|
o_X2U_DATA => s_opb_out
|
);
|
);
|
|
|
|
|
|
|
MAP_U2X_Data : process(i_nReset, i_IFCLK)
|
|
variable count : integer range 0 to 7;
|
|
begin
|
|
if ( i_nReset = '0') then
|
|
count := 0;
|
|
s_U2X_FIFO_WR_EN <= '0';
|
|
s_U2X_extracted <= '0';
|
|
rst_header_Reg(s_U2X_HeaderReg);
|
|
|
|
elsif rising_edge(i_IFCLK) then
|
|
if (s_U2X_setHeader = EOT ) then
|
|
count := 0;
|
|
s_U2X_FIFO_WR_EN <= '0';
|
|
s_U2X_extracted <= '0';
|
|
else
|
|
if count < HEAD_EXT_VAL then
|
|
wr_header_Reg_element(count,s_dbus_in,s_U2X_HeaderReg);
|
|
count := count+1;
|
|
s_U2X_FIFO_WR_EN <= '0';
|
|
else
|
|
s_U2X_FIFO_WR_EN <= s_U2X_WR_EN;
|
|
s_U2X_extracted <= '1';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process MAP_U2X_Data;
|
|
|
|
|
|
|
|
--
|
|
--MAP_U2X_Data : process(i_nReset, i_IFCLK)
|
|
-- variable count integer range 0 to 7;
|
|
-- begin
|
|
-- if ( i_nReset = '0') then
|
|
-- s_U2X_HeaderReg <= (others => '0');
|
|
-- count := 0;
|
|
-- s_U2X_FIFO_WR_EN <= '0';
|
|
-- s_U2X_extracted <= '0';
|
|
--
|
|
-- elsif rising_edge(i_IFCLK) then
|
|
-- if (s_U2X_setHeader = EOT ) then
|
|
-- count := '0';
|
|
-- s_U2X_FIFO_WR_EN <= '0';
|
|
-- s_U2X_extracted <= '0';
|
|
-- else
|
|
-- if count < HEAD_EXT_VAL then
|
|
-- s_U2X_HeaderReg(2*count) <= s_dbus_in(BYTE-1 downto 0);
|
|
-- s_U2X_HeaderReg((2*count)+1) <= s_dbus_in((2*BYTE)-1 downto BYTE);
|
|
-- count := count+1;
|
|
-- s_U2X_FIFO_WR_EN <= '0';
|
|
-- else
|
|
-- s_U2X_FIFO_WR_EN <= s_U2X_WR_EN;
|
|
-- s_U2X_extracted <= '1';
|
|
-- end if;
|
|
-- end if;
|
|
-- end if;
|
|
--end process MAP_U2X_Data;
|
|
|
|
|
|
MAP_X2U_Data : process(i_nReset, i_SYSCLK)
|
|
variable count : integer range 0 to 7;
|
|
begin
|
|
if ( i_nReset = '0') then
|
|
count := 0;
|
|
s_X2U_FIFO_RD_EN <= '0';
|
|
|
|
elsif rising_edge(i_IFCLK) then
|
|
if (s_X2U_setHeader = EOT ) then
|
|
count := 0;
|
|
s_X2U_FIFO_RD_EN <= '0';
|
|
else
|
|
if count < HEAD_EXT_VAL then
|
|
rd_header_Reg_element(count,s_X2U_HeaderReg,s_dbus_out);
|
|
count := count+1;
|
|
s_X2U_FIFO_RD_EN <= '0';
|
|
else
|
|
s_X2U_FIFO_RD_EN <= s_X2U_RD_EN;
|
|
s_dbus_out <= s_X2U_FIFO_dbus_out;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
|
|
end process MAP_X2U_Data;
|
|
|
|
|
|
|
|
--
|
--
|
--uart : miniUART
|
--uart : miniUART
|
-- port map (
|
-- port map (
|
-- SysClk => i_SYSCLK,
|
-- SysClk => i_SYSCLK,
|
-- Reset => i_nReset,
|
-- Reset => i_nReset,
|
