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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [gpif_com.vhd] - Diff between revs 14 and 18

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--  You should have received a copy of the GNU General Public License
 
--  You should have received a copy of the GNU General Public License
 
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
--
 
--
 
--  URL to the project description: 
--  URL to the project description: 
--    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
 
--    http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
 
----------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--
 
--
 
--  Author:  Andreas Habegger, Christoph Zimmermann
 
--  Author:  Andreas Habegger, Christoph Zimmermann
 
--  Date of creation: 8. April 2009
 
--  Date of creation: 8. April 2009
 
--  Description:
 
--  Description:
 
--      GECKO3COM defines the communication between the GECKO3main and a USB Master e.g. a computer.
 
--    GECKO3COM defines the communication between the GECKO3main and a USB
 
--              This file is the top module, it instantiates all required submodules and connects them 
--    Master e.g. a computer.
 
--              together.
 
 
 
--
 
--
 
--  Target Devices:     Xilinx Spartan3 FPGA's (usage of BlockRam in the Datapath)
 
--    This file is the top module, it instantiates all required submodules and
 
 
 
--    connects them together.
 
 
 
--
 
 
 
--  Target Devices:     Xilinx Spartan3 FPGA's
 
 
 
--                      (usage of BlockRam in the Datapath)
 
--  Tool versions:      11.1
 
--  Tool versions:      11.1
 
--  Dependencies:
 
--  Dependencies:
 
--
 
--
 
----------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
 
 
 
library ieee;
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_arith.all;
 
use ieee.std_logic_arith.all;
 
 
 
 
 
library work;
 
library work;
 
use work.GECKO3COM_defines.all;
 
use work.GECKO3COM_defines.all;
 
use work.USB_TMC_cmp.all;
 
 
 
 
 
 
 
 
 
 
 
entity gpif_com is
 
entity gpif_com is
 
  port (
 
  port (
 
    i_nReset,
 
    -- interface signals to higher level
 
    i_IFCLK,                                                                     -- GPIF CLK (GPIF is Master and provides the clock)
 
    i_nReset  : in  std_logic;          -- asynchronous active low reset
 
    i_SYSCLK,                                                                    -- FPGA System CLK
 
    i_SYSCLK  : in  std_logic;          -- FPGA System CLK
 
    i_WRU,                              -- write from GPIF
 
 
 
    i_RDYU        : in          std_logic;        -- GPIF is ready
 
 
 
    o_WRX,                              -- To write to GPIF
 
 
 
    o_RDYX    : out     std_logic;      -- IP Core is ready
 
 
 
    o_ABORT   : out   std_logic;  -- Abort detected, you have to flush the data
 
    o_ABORT   : out   std_logic;  -- Abort detected, you have to flush the data
 
    o_RX,                            -- controll LED rx
 
    o_RX      : out std_logic;          -- controll LED rx
 
    o_TX : out          std_logic;               -- controll LED tx
 
    o_TX : out          std_logic;               -- controll LED tx
 
 
 
    i_RD_EN   : in  std_logic;          -- read enable
 
 
 
    o_EMPTY   : out std_logic;          -- receive fifo empty
 
 
 
    o_RX_DATA : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);  -- receive data
 
 
 
    i_WR_EN   : in  std_logic;          -- write enable
 
 
 
    o_FULL    : out std_logic;          -- send fifo full
 
 
 
    i_TX_DATA : in  std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);  -- send data
 
 
 
 
 
 
 
    -- GPIF connections, to be connected to FPGA pins
 
 
 
    i_IFCLK    : in    std_logic;       -- GPIF CLK (GPIF is Master and provides the clock)
 
 
 
    i_WRU      : in    std_logic;       -- write from GPIF
 
 
 
    i_RDYU     : in    std_logic;       -- GPIF is ready
 
 
 
    o_WRX      : out   std_logic;       -- To write to GPIF
 
 
 
    o_RDYX     : out   std_logic;       -- IP Core is ready
 
    b_gpif_bus    : inout       std_logic_vector(SIZE_DBUS_GPIF-1 downto 0));  -- bidirect data bus
 
    b_gpif_bus    : inout       std_logic_vector(SIZE_DBUS_GPIF-1 downto 0));  -- bidirect data bus
 
end gpif_com;
 
end gpif_com;
 
 
 
 
 
 
 
 
 
 
 
 
 
architecture structure of gpif_com is
 
architecture structure of gpif_com is
 
 
 
 
 
  -- interconection signals
 
  -- interconection signals
 
 
 
 
 
  signal s_FIFOrst           : std_logic;
 
  signal s_FIFOrst, s_WRX, s_RDYX      : std_logic;
 
 
 
 
 
  signal s_ABORT_FSM, s_ABORT_TMP  : std_logic;
 
  signal s_ABORT_FSM, s_ABORT_TMP  : std_logic;
 
  signal s_RX_FSM, s_RX_TMP  : std_logic;
 
  signal s_RX_FSM, s_RX_TMP  : std_logic;
 
  signal s_TX_FSM, s_TX_TMP  : std_logic;
 
  signal s_TX_FSM, s_TX_TMP  : std_logic;
 
 
 
 
Line 78... Line 89... 
         s_U2X_RD_EN,
 
         s_U2X_RD_EN,
 
         s_U2X_FULL,
 
         s_U2X_FULL,
 
         s_U2X_AM_FULL,
 
         s_U2X_AM_FULL,
 
         s_U2X_EMPTY,
 
         s_U2X_EMPTY,
 
         s_U2X_AM_EMPTY : std_logic;
 
         s_U2X_AM_EMPTY : std_logic;
 
 
 
  signal s_U2X_DATA     : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
 
 
 
 
     -- Xilinx to USB (X2U)
 
     -- Xilinx to USB (X2U)
 
  signal s_X2U_WR_EN,
 
  signal s_X2U_WR_EN,
 
         s_X2U_RD_EN,
 
         s_X2U_RD_EN,
 
         s_X2U_FULL,
 
         s_X2U_FULL,
 
         s_X2U_AM_FULL,
 
         s_X2U_AM_FULL,
 
         s_X2U_EMPTY,
 
         s_X2U_EMPTY,
 
         s_X2U_AM_EMPTY : std_logic;
 
         s_X2U_AM_EMPTY : std_logic;
 
 
 
  signal s_X2U_DATA     : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
 
 
 
 
  -------------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- data bus
 
  -- data bus
 
  -------------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
 
 
 
 
  -- data signals
 
  -- data signals
 
  signal s_dbus_trans_dir     : std_logic;
 
  signal s_dbus_trans_dir     : std_logic;
 
        signal s_dbus_in  : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
        signal s_dbus_in  : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
        signal s_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
        signal s_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
 
 
 
 
        signal s_opb_in : std_logic_vector(SIZE_DBUS_FPGA-1 downto 0);
 
 
 
        signal s_opb_out        : std_logic_vector(SIZE_DBUS_FPGA-1 downto 0);
 
 
 
 
 
 
 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- COMPONENTS
 
  -- COMPONENTS
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
 
 
 
 
  -- FSM GPIF
 
  -- FSM GPIF
Line 130... Line 139... 
  end component;
 
  end component;
 
 
 
 
 
  -- FIFO dualclock to cross the clock domain between the GPIF and the FPGA
 
  -- FIFO dualclock to cross the clock domain between the GPIF and the FPGA
 
  component fifo_dualclock
 
  component fifo_dualclock
 
  port (
 
  port (
 
    i_din          : IN  std_logic_VECTOR(SIZE_DBUS_GPIF-1 downto 0);
 
      i_din          : IN  std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
    i_rd_clk       : IN  std_logic;
 
    i_rd_clk       : IN  std_logic;
 
    i_rd_en        : IN  std_logic;
 
    i_rd_en        : IN  std_logic;
 
    i_rst          : IN  std_logic;
 
    i_rst          : IN  std_logic;
 
    i_wr_clk       : IN  std_logic;
 
    i_wr_clk       : IN  std_logic;
 
    i_wr_en        : IN  std_logic;
 
    i_wr_en        : IN  std_logic;
 
    o_almost_empty : OUT std_logic;
 
    o_almost_empty : OUT std_logic;
 
    o_almost_full  : OUT std_logic;
 
    o_almost_full  : OUT std_logic;
 
    o_dout         : OUT std_logic_VECTOR(SIZE_DBUS_GPIF-1 downto 0);
 
      o_dout         : OUT std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
    o_empty        : OUT std_logic;
 
    o_empty        : OUT std_logic;
 
    o_full         : OUT std_logic);
 
    o_full         : OUT std_logic);
 
  end component;
 
  end component;
 
 
 
 
 
 
 
 
Line 160... Line 169... 
    i_rst          => s_FIFOrst,
 
    i_rst          => s_FIFOrst,
 
    i_wr_clk       => i_IFCLK ,
 
    i_wr_clk       => i_IFCLK ,
 
    i_wr_en        => s_U2X_WR_EN,
 
    i_wr_en        => s_U2X_WR_EN,
 
    o_almost_empty => s_U2X_AM_EMPTY,
 
    o_almost_empty => s_U2X_AM_EMPTY,
 
    o_almost_full  => s_U2X_AM_FULL,
 
    o_almost_full  => s_U2X_AM_FULL,
 
    o_dout         => s_opb_in,
 
      o_dout         => s_U2X_DATA,
 
    o_empty        => s_U2X_EMPTY,
 
    o_empty        => s_U2X_EMPTY,
 
    o_full         => s_U2X_FULL
 
    o_full         => s_U2X_FULL
 
  );
 
  );
 
 
 
 
 
 
 
 
 
  F_OUT : fifo_dualclock
 
  F_OUT : fifo_dualclock
 
  port map (
 
  port map (
 
    i_din          => s_opb_out,
 
      i_din          => s_X2U_DATA,
 
    i_rd_clk       => i_IFCLK,
 
    i_rd_clk       => i_IFCLK,
 
    i_rd_en        => s_X2U_RD_EN,
 
    i_rd_en        => s_X2U_RD_EN,
 
    i_rst          => s_FIFOrst,
 
    i_rst          => s_FIFOrst,
 
    i_wr_clk       => i_SYSCLK,
 
    i_wr_clk       => i_SYSCLK,
 
    i_wr_en        => s_X2U_WR_EN,
 
    i_wr_en        => s_X2U_WR_EN,
Line 196... Line 205... 
                i_X2U_EMPTY             => s_X2U_EMPTY,
 
                i_X2U_EMPTY             => s_X2U_EMPTY,
 
                o_U2X_WR_EN             => s_U2X_WR_EN,
 
                o_U2X_WR_EN             => s_U2X_WR_EN,
 
                o_X2U_RD_EN             => s_X2U_RD_EN,
 
                o_X2U_RD_EN             => s_X2U_RD_EN,
 
                o_FIFOrst               => s_FIFOrst,
 
                o_FIFOrst               => s_FIFOrst,
 
                o_bus_trans_dir => s_dbus_trans_dir,
 
                o_bus_trans_dir => s_dbus_trans_dir,
 
                o_WRX                           => o_WRX,
 
      o_WRX           => s_WRX,
 
                o_RDYX                  => o_RDYX,
 
      o_RDYX          => s_RDYX,
 
    o_ABORT     => s_ABORT_FSM,
 
    o_ABORT     => s_ABORT_FSM,
 
                o_RX               => o_RX,
 
      o_RX            => s_RX_FSM,
 
                o_TX               => o_TX,
 
      o_TX            => s_TX_FSM
 
        );
 
        );
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  s_U2X_RD_EN  <= i_RD_EN;
 
 
 
  o_EMPTY   <= s_U2X_EMPTY;
 
 
 
  o_RX_DATA <= s_U2X_DATA;
 
 
 
 
 
 
 
  s_X2U_WR_EN <= i_WR_EN;
 
 
 
  o_FULL    <= s_X2U_FULL;
 
 
 
  s_X2U_DATA <= i_TX_DATA;
 
 
 
 
 
 
 
  o_WRX <= s_WRX;
 
 
 
  o_RDYX <= s_RDYX;
 
 
 
 
 
  -- Double buffer the ABORT, RX and TX signal to avoid metastability
 
  -- Double buffer the ABORT, RX and TX signal to avoid metastability
 
  double_buf_sig : process (i_SYSCLK, i_nReset)
 
  double_buf_sig : process (i_SYSCLK, i_nReset)
 
  begin
 
  begin
 
    if i_nReset = '0' then
 
    if i_nReset = '0' then
 
      o_ABORT <= '0';
 
      o_ABORT <= '0';
 
      s_ABORT_TMP <= '0';
 
      s_ABORT_TMP <= '0';
 
      s_TX_FSM <= '0';
 
      o_TX        <= '0';
 
      s_TX_TMP <= '0';
 
 
 
      s_RX_FSM <= '0';
 
 
 
      s_TX_TMP <= '0';
 
      s_TX_TMP <= '0';
 
    elsif rising_edge(i_SYSCLK)
 
      o_RX        <= '0';
 
 
 
      s_RX_TMP    <= '0';
 
 
 
    elsif rising_edge(i_SYSCLK) then
 
      o_ABORT <= s_ABORT_TMP;
 
      o_ABORT <= s_ABORT_TMP;
 
      s_ABORT_TMP <= s_ABORT_FSM;
 
      s_ABORT_TMP <= s_ABORT_FSM;
 
      o_TX <= s_TX_TMP;
 
      o_TX <= s_TX_TMP;
 
      s_TX_TMP <= s_TX_FSM;
 
      s_TX_TMP <= s_TX_FSM;
 
      o_RX <= s_RX_TMP;
 
      o_RX <= s_RX_TMP;
Line 235... Line 257... 
  -- inputs : s_bus_trans_dir
 
  -- inputs : s_bus_trans_dir
 
  -- outputs: 
  -- outputs: 
  bus_access : process (s_dbus_trans_dir, s_dbus_out)
 
  bus_access : process (s_dbus_trans_dir, s_dbus_out)
 
  begin  -- process bus_access
 
  begin  -- process bus_access
 
    if s_dbus_trans_dir = '1' then
 
    if s_dbus_trans_dir = '1' then
 
      b_gpifbus <= s_dbus_out;
 
      b_gpif_bus <= s_dbus_out;
 
    else
 
    else
 
      b_gpifbus <= (others => 'Z');
 
      b_gpif_bus <= (others => 'Z');
 
    end if;
 
    end if;
 
  end process bus_access;
 
  end process bus_access;
 
 
 
 
 
  s_dbus_in <= b_gpifbus;
 
  s_dbus_in <= b_gpif_bus;
 
 
 
 
 
end structure;
 
end structure;
 
 
 
 
 
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