| Line 57... |
Line 57... |
o_RX : out std_logic; -- controll LED rx
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o_RX : out std_logic; -- controll LED rx
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o_TX : out std_logic; -- controll LED tx
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o_TX : out std_logic; -- controll LED tx
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i_RD_EN : in std_logic; -- read enable
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i_RD_EN : in std_logic; -- read enable
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o_EMPTY : out std_logic; -- receive fifo empty
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o_EMPTY : out std_logic; -- receive fifo empty
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o_RX_DATA : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); -- receive data
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o_RX_DATA : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); -- receive data
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i_EOM : in std_logic;
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i_WR_EN : in std_logic; -- write enable
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i_WR_EN : in std_logic; -- write enable
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o_FULL : out std_logic; -- send fifo full
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o_FULL : out std_logic; -- send fifo full
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i_TX_DATA : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); -- send data
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i_TX_DATA : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); -- send data
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|
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-- GPIF connections, to be connected to FPGA pins
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-- GPIF connections, to be connected to FPGA pins
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| Line 81... |
Line 82... |
signal s_FIFOrst, s_WRX, s_RDYX : std_logic;
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signal s_FIFOrst, s_WRX, s_RDYX : std_logic;
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|
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signal s_ABORT_FSM, s_ABORT_TMP : std_logic;
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signal s_ABORT_FSM, s_ABORT_TMP : std_logic;
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signal s_RX_FSM, s_RX_TMP : std_logic;
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signal s_RX_FSM, s_RX_TMP : std_logic;
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signal s_TX_FSM, s_TX_TMP : std_logic;
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signal s_TX_FSM, s_TX_TMP : std_logic;
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signal s_EOM, s_EOM_TMP : std_logic; -- End of message
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signal s_X2U_FULL_IFCLK, s_X2U_FULL_TMP : std_logic;
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|
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-- USB to Xilinx (U2X)
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-- USB to Xilinx (U2X)
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signal s_U2X_WR_EN,
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signal s_U2X_WR_EN,
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s_U2X_RD_EN,
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s_U2X_RD_EN,
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s_U2X_FULL,
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s_U2X_FULL,
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| Line 116... |
Line 119... |
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
|
|
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-- FSM GPIF
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-- FSM GPIF
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component gpif_com_fsm
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component gpif_com_fsm
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port (
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port (
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i_nReset,
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i_nReset : in std_logic;
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i_IFCLK, -- GPIF CLK (is Master)
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i_IFCLK : in std_logic;
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i_WRU, -- write from GPIF
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i_WRU : in std_logic;
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i_RDYU : in std_logic; -- GPIF is ready
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i_RDYU : in std_logic;
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i_U2X_FULL,
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i_EOM : in std_logic;
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i_U2X_AM_FULL, -- signals for IN FIFO
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i_U2X_FULL : in std_logic;
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i_X2U_AM_EMPTY,
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i_U2X_AM_FULL : in std_logic;
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i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO
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i_X2U_FULL_IFCLK : in std_logic;
|
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i_X2U_AM_EMPTY : in std_logic;
|
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i_X2U_EMPTY : in std_logic;
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o_bus_trans_dir : out std_logic;
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o_bus_trans_dir : out std_logic;
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o_U2X_WR_EN, -- signals for IN FIFO
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o_U2X_WR_EN : out std_logic;
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o_X2U_RD_EN, -- signals for OUT FIFO
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o_X2U_RD_EN : out std_logic;
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o_FIFOrst,
|
o_FIFOrst : out std_logic;
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o_WRX, -- To write to GPIF
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o_WRX : out std_logic;
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o_RDYX : out std_logic; -- Core is ready
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o_RDYX : out std_logic;
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o_ABORT : out std_logic; -- abort condition detected. we have to flush the data
|
o_ABORT : out std_logic;
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o_RX,
|
o_RX : out std_logic;
|
o_TX : out std_logic --
|
o_TX : out std_logic);
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);
|
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end component;
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end component;
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|
|
-- FIFO dualclock to cross the clock domain between the GPIF and the FPGA
|
-- FIFO dualclock to cross the clock domain between the GPIF and the FPGA
|
component fifo_dualclock
|
component fifo_dualclock
|
port (
|
port (
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| Line 197... |
Line 201... |
port map (
|
port map (
|
i_nReset => i_nReset,
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i_nReset => i_nReset,
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i_IFCLK => i_IFCLK,
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i_IFCLK => i_IFCLK,
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i_WRU => i_WRU,
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i_WRU => i_WRU,
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i_RDYU => i_RDYU,
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i_RDYU => i_RDYU,
|
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i_EOM => s_EOM,
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i_U2X_FULL => s_U2X_FULL,
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i_U2X_FULL => s_U2X_FULL,
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i_U2X_AM_FULL => s_U2X_AM_FULL,
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i_U2X_AM_FULL => s_U2X_AM_FULL,
|
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i_X2U_FULL_IFCLK => s_X2U_FULL_IFCLK,
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i_X2U_AM_EMPTY => s_X2U_AM_EMPTY,
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i_X2U_AM_EMPTY => s_X2U_AM_EMPTY,
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i_X2U_EMPTY => s_X2U_EMPTY,
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i_X2U_EMPTY => s_X2U_EMPTY,
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o_U2X_WR_EN => s_U2X_WR_EN,
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o_U2X_WR_EN => s_U2X_WR_EN,
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o_X2U_RD_EN => s_X2U_RD_EN,
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o_X2U_RD_EN => s_X2U_RD_EN,
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o_FIFOrst => s_FIFOrst,
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o_FIFOrst => s_FIFOrst,
|
| Line 245... |
Line 251... |
o_RX <= s_RX_TMP;
|
o_RX <= s_RX_TMP;
|
s_RX_TMP <= s_RX_FSM;
|
s_RX_TMP <= s_RX_FSM;
|
end if;
|
end if;
|
end process double_buf_sig;
|
end process double_buf_sig;
|
|
|
|
-- Double buffer the ABORT, RX and TX signal to avoid metastability
|
|
double_buf_ifclk : process (i_IFCLK, i_nReset)
|
|
begin
|
|
if i_nReset = '0' then
|
|
s_X2U_FULL_TMP <= '0';
|
|
s_X2U_FULL_IFCLK <= '0';
|
|
elsif rising_edge(i_IFCLK) then
|
|
s_EOM <= s_EOM_TMP;
|
|
s_EOM_TMP <= i_EOM;
|
|
s_X2U_FULL_IFCLK <= s_X2U_FULL_TMP;
|
|
s_X2U_FULL_TMP <= s_X2U_FULL;
|
|
end if;
|
|
end process double_buf_ifclk;
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Data bus access
|
-- Data bus access
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
