Line 82... |
Line 82... |
signal s_FIFOrst, s_WRX, s_RDYX : std_logic;
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signal s_FIFOrst, s_WRX, s_RDYX : std_logic;
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signal s_ABORT_FSM, s_ABORT_TMP : std_logic;
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signal s_ABORT_FSM, s_ABORT_TMP : std_logic;
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signal s_RX_FSM, s_RX_TMP : std_logic;
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signal s_RX_FSM, s_RX_TMP : std_logic;
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signal s_TX_FSM, s_TX_TMP : std_logic;
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signal s_TX_FSM, s_TX_TMP : std_logic;
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signal s_EOM, s_EOM_TMP : std_logic; -- End of message
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signal s_EOM, s_EOM_TMP, s_EOM_FF : std_logic; -- End of message
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signal s_X2U_FULL_IFCLK, s_X2U_FULL_TMP : std_logic;
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signal s_X2U_FULL_IFCLK, s_X2U_FULL_TMP : std_logic;
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-- USB to Xilinx (U2X)
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-- USB to Xilinx (U2X)
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signal s_U2X_WR_EN,
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signal s_U2X_WR_EN,
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s_U2X_RD_EN,
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s_U2X_RD_EN,
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Line 201... |
Line 201... |
port map (
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port map (
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i_nReset => i_nReset,
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i_nReset => i_nReset,
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i_IFCLK => i_IFCLK,
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i_IFCLK => i_IFCLK,
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i_WRU => i_WRU,
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i_WRU => i_WRU,
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i_RDYU => i_RDYU,
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i_RDYU => i_RDYU,
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i_EOM => s_EOM,
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i_EOM => s_EOM_FF,
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i_U2X_FULL => s_U2X_FULL,
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i_U2X_FULL => s_U2X_FULL,
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i_U2X_AM_FULL => s_U2X_AM_FULL,
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i_U2X_AM_FULL => s_U2X_AM_FULL,
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i_X2U_FULL_IFCLK => s_X2U_FULL_IFCLK,
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i_X2U_FULL_IFCLK => s_X2U_FULL_IFCLK,
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i_X2U_AM_EMPTY => s_X2U_AM_EMPTY,
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i_X2U_AM_EMPTY => s_X2U_AM_EMPTY,
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i_X2U_EMPTY => s_X2U_EMPTY,
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i_X2U_EMPTY => s_X2U_EMPTY,
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Line 251... |
Line 251... |
o_RX <= s_RX_TMP;
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o_RX <= s_RX_TMP;
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s_RX_TMP <= s_RX_FSM;
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s_RX_TMP <= s_RX_FSM;
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end if;
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end if;
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end process double_buf_sig;
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end process double_buf_sig;
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-- Double buffer the ABORT, RX and TX signal to avoid metastability
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-- Double buffer the s_EOM and s_X2U_FULL_IFCLK signal to avoid metastability
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double_buf_ifclk : process (i_IFCLK, i_nReset)
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double_buf_ifclk : process (i_IFCLK, i_nReset)
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begin
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begin
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if i_nReset = '0' then
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if i_nReset = '0' then
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s_X2U_FULL_TMP <= '0';
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s_X2U_FULL_TMP <= '0';
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s_X2U_FULL_IFCLK <= '0';
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s_X2U_FULL_IFCLK <= '0';
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Line 265... |
Line 265... |
s_X2U_FULL_IFCLK <= s_X2U_FULL_TMP;
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s_X2U_FULL_IFCLK <= s_X2U_FULL_TMP;
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s_X2U_FULL_TMP <= s_X2U_FULL;
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s_X2U_FULL_TMP <= s_X2U_FULL;
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end if;
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end if;
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end process double_buf_ifclk;
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end process double_buf_ifclk;
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-- purpose: EOM bit flip-flop
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-- type : sequential
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-- inputs : i_IFCLK, i_nReset, s_EOM, s_X2U_EMPTY
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-- outputs: s_EOM_FF
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EOM_FF: process (i_IFCLK, i_nReset)
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begin -- process EOM_FF
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if i_nReset = '0' then -- asynchronous reset (active low)
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s_EOM_FF <= '0';
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elsif i_IFCLK'event and i_IFCLK = '1' then -- rising clock edge
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if s_EOM = '1' then
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s_EOM_FF <= '1';
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end if;
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if s_X2U_EMPTY = '1' then
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s_EOM_FF <= '0';
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end if;
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end if;
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end process EOM_FF;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Data bus access
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-- Data bus access
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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