| Line 102... |
Line 102... |
s_X2U_AM_FULL,
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s_X2U_AM_FULL,
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s_X2U_EMPTY,
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s_X2U_EMPTY,
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s_X2U_AM_EMPTY : std_logic;
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s_X2U_AM_EMPTY : std_logic;
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signal s_X2U_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_X2U_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_dbus_out_mux_sel : std_logic;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- data bus
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-- data bus
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- data signals
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-- data signals
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signal s_dbus_trans_dir : std_logic;
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signal s_dbus_trans_dir : std_logic;
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signal s_dbus_in : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_dbus_in : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_dbus_out_fifo : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_fifo_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_fifo_old : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- COMPONENTS
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-- COMPONENTS
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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| Line 126... |
Line 130... |
i_WRU : in std_logic;
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i_WRU : in std_logic;
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i_RDYU : in std_logic;
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i_RDYU : in std_logic;
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i_EOM : in std_logic;
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i_EOM : in std_logic;
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i_U2X_FULL : in std_logic;
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i_U2X_FULL : in std_logic;
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i_U2X_AM_FULL : in std_logic;
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i_U2X_AM_FULL : in std_logic;
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i_X2U_FULL_IFCLK : in std_logic;
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i_X2U_AM_EMPTY : in std_logic;
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i_X2U_AM_EMPTY : in std_logic;
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i_X2U_EMPTY : in std_logic;
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i_X2U_EMPTY : in std_logic;
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o_dbus_out_mux_sel : out std_logic;
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o_bus_trans_dir : out std_logic;
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o_bus_trans_dir : out std_logic;
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o_U2X_WR_EN : out std_logic;
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o_U2X_WR_EN : out std_logic;
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o_X2U_RD_EN : out std_logic;
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o_X2U_RD_EN : out std_logic;
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o_FIFOrst : out std_logic;
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o_FIFOrst : out std_logic;
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o_WRX : out std_logic;
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o_WRX : out std_logic;
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| Line 189... |
Line 193... |
i_rst => s_FIFOrst,
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i_rst => s_FIFOrst,
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i_wr_clk => i_SYSCLK,
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i_wr_clk => i_SYSCLK,
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i_wr_en => s_X2U_WR_EN,
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i_wr_en => s_X2U_WR_EN,
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o_almost_empty => s_X2U_AM_EMPTY,
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o_almost_empty => s_X2U_AM_EMPTY,
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o_almost_full => s_X2U_AM_FULL,
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o_almost_full => s_X2U_AM_FULL,
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o_dout => s_dbus_out_fifo,
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o_dout => s_fifo_out,
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o_empty => s_X2U_EMPTY,
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o_empty => s_X2U_EMPTY,
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o_full => s_X2U_FULL
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o_full => s_X2U_FULL
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);
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);
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| Line 205... |
Line 209... |
i_RDYU => i_RDYU,
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i_RDYU => i_RDYU,
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--i_EOM => s_EOM,
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--i_EOM => s_EOM,
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i_EOM => s_EOM_FF,
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i_EOM => s_EOM_FF,
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i_U2X_FULL => s_U2X_FULL,
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i_U2X_FULL => s_U2X_FULL,
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i_U2X_AM_FULL => s_U2X_AM_FULL,
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i_U2X_AM_FULL => s_U2X_AM_FULL,
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i_X2U_FULL_IFCLK => s_X2U_FULL_IFCLK,
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i_X2U_AM_EMPTY => s_X2U_AM_EMPTY,
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i_X2U_AM_EMPTY => s_X2U_AM_EMPTY,
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i_X2U_EMPTY => s_X2U_EMPTY,
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i_X2U_EMPTY => s_X2U_EMPTY,
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o_U2X_WR_EN => s_U2X_WR_EN,
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o_U2X_WR_EN => s_U2X_WR_EN,
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o_X2U_RD_EN => s_X2U_RD_EN,
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o_X2U_RD_EN => s_X2U_RD_EN,
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o_dbus_out_mux_sel => s_dbus_out_mux_sel,
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o_FIFOrst => s_FIFOrst,
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o_FIFOrst => s_FIFOrst,
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o_bus_trans_dir => s_dbus_trans_dir,
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o_bus_trans_dir => s_dbus_trans_dir,
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o_WRX => s_WRX,
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o_WRX => s_WRX,
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o_RDYX => s_RDYX,
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o_RDYX => s_RDYX,
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o_ABORT => s_ABORT_FSM,
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o_ABORT => s_ABORT_FSM,
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| Line 256... |
Line 260... |
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-- Double buffer the s_EOM and s_X2U_FULL_IFCLK signal to avoid metastability
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-- Double buffer the s_EOM and s_X2U_FULL_IFCLK signal to avoid metastability
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double_buf_ifclk : process (i_IFCLK, i_nReset)
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double_buf_ifclk : process (i_IFCLK, i_nReset)
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begin
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begin
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if i_nReset = '0' then
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if i_nReset = '0' then
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s_X2U_FULL_TMP <= '0';
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s_EOM <= '0';
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s_X2U_FULL_IFCLK <= '0';
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elsif rising_edge(i_IFCLK) then
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elsif rising_edge(i_IFCLK) then
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s_EOM <= s_EOM_TMP;
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s_EOM <= s_EOM_TMP;
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s_EOM_TMP <= i_EOM;
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s_EOM_TMP <= i_EOM;
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s_X2U_FULL_IFCLK <= s_X2U_FULL_TMP;
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s_X2U_FULL_TMP <= s_X2U_FULL;
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end if;
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end if;
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end process double_buf_ifclk;
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end process double_buf_ifclk;
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--purpose: EOM bit flip-flop
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--purpose: EOM bit flip-flop
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--type : sequential
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--type : sequential
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| Line 309... |
Line 310... |
begin
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begin
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if rising_edge(i_IFCLK) then
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if rising_edge(i_IFCLK) then
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s_dbus_in <= b_gpif_bus;
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s_dbus_in <= b_gpif_bus;
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if s_X2U_RD_EN = '1' then
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if s_X2U_RD_EN = '1' then
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s_dbus_out <= s_dbus_out_fifo;
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s_fifo_old <= s_fifo_out;
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end if;
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end if;
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end if;
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end if;
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end process buf_input;
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end process buf_input;
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-- purpose: multiplexer to select two older copies of fifo data
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-- type : combinational
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-- inputs : s_dbus_out_mux_sel, s_fifo_old, s_fifo_out
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-- outputs: s_dbus_out
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dbus_out_mux: process (s_dbus_out_mux_sel, s_fifo_old, s_fifo_out)
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begin -- process dbus_out_mux
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case s_dbus_out_mux_sel is
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when '0' => s_dbus_out <= s_fifo_out;
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when '1' => s_dbus_out <= s_fifo_old;
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when others => s_dbus_out <= s_fifo_out;
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end case;
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end process dbus_out_mux;
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end structure;
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end structure;
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No newline at end of file
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No newline at end of file
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