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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [gpif_com_fsm.vhd] - Diff between revs 18 and 19

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Rev 18 Rev 19
Line 67... Line 67... 
    o_ABORT         : out std_logic;  -- abort condition detected. we have to flush the data
 
    o_ABORT         : out std_logic;  -- abort condition detected. we have to flush the data
 
    o_RX            : out std_logic;
 
    o_RX            : out std_logic;
 
    o_TX            : out std_logic     --
 
    o_TX            : out std_logic     --
 
    );
 
    );
 
 
 
 
 
  -- XST specific synthesize attributes
 
 
 
  attribute safe_implementation: string;
 
 
 
  attribute safe_recovery_state: string;
 
 
 
 
 
 
 
  attribute safe_implementation of gpif_com_fsm : entity is "yes";
 
 
 
 
 
 
 
end gpif_com_fsm;
 
end gpif_com_fsm;
 
 
 
 
 
 
 
 
 
 
 
 
 
architecture fsm of gpif_com_fsm is
 
architecture fsm of gpif_com_fsm is
 
 
 
 
 
 
 
  -- XST specific synthesize attributes
 
 
 
  attribute safe_implementation: string;
 
 
 
  attribute safe_recovery_state: string;
 
 
 
 
 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- FSM
 
  -- FSM
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
 
 
 
 
  type   t_busAccess is (readFromGPIF, writeToGPIF);
 
  type   t_busAccess is (readFromGPIF, writeToGPIF);
 
  signal s_bus_trans_dir : t_busAccess;
 
  signal s_bus_trans_dir : t_busAccess;
 
 
 
 
 
 
 
 
 
  type t_fsmState is (rst, idle,        -- controll states
 
  type t_fsmState is (rst, idle,        -- controll states
 
                      inRQ, inACK, inTrans, inThrot,
 
                      inRQ, inACK, inWait, inTrans, inThrot,
 
                      inThrotEnd, endInTrans,  -- in com states
 
                      inThrotBreak,inThrotBreak2, inThrotEnd, endInTrans,  -- in com states
 
                      outRQ, outTrans, outWait, endOutTrans);  -- out com states
 
                      outRQ, outTrans, outWait, endOutTrans);  -- out com states
 
 
 
 
 
 
 
 
 
 
 
 
 
  signal pr_state, nx_state : t_fsmState;
 
  signal pr_state, nx_state : t_fsmState;
 
  -- XST specific synthesize attributes
 
  -- XST specific synthesize attributes
 
  attribute safe_recovery_state of pr_state : signal is "idle";
 
  attribute safe_recovery_state of pr_state : signal is "idle";
 
  attribute safe_recovery_state of nx_state : signal is "idle";
 
  attribute safe_implementation of pr_state : signal is "yes";
 
 
 
 
 
 
 
 
 
 
 
 
 
  -- interconection signals
 
  -- interconection signals
 
  signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;
 
  signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;
 
 
 
 
Line 111... Line 111... 
  -- Xilinx to USB (X2U)
 
  -- Xilinx to USB (X2U)
 
  signal s_X2U_RD_EN : std_logic;
 
  signal s_X2U_RD_EN : std_logic;
 
 
 
 
 
begin
 
begin
 
 
 
 
 
 
 
 
 
 
 
 
 
  o_FIFOrst       <= s_FIFOrst;
 
  o_FIFOrst       <= s_FIFOrst;
 
  o_X2U_RD_EN     <= s_X2U_RD_EN;
 
  o_X2U_RD_EN     <= s_X2U_RD_EN;
 
  o_WRX           <= s_WRX;
 
  o_WRX           <= s_WRX;
 
  o_RDYX          <= s_RDYX;
 
  o_RDYX          <= s_RDYX;
 
  o_U2X_WR_EN     <= s_U2X_WR_EN;
 
  o_U2X_WR_EN     <= s_U2X_WR_EN;
Line 126... Line 128... 
  -- FSM GPIF
 
  -- FSM GPIF
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
 
 
 
 
  -- state reg
 
  -- state reg
 
  action : process(i_IFCLK, i_nReset)
 
  action : process(i_IFCLK, i_nReset)
 
    variable v_setup : integer range 0 to 15;
 
 
 
  begin
 
  begin
 
 
 
 
 
    if i_nReset = '0' then
 
    if i_nReset = '0' then
 
      pr_state <= rst;
 
      pr_state <= rst;
 
 
 
 
Line 139... Line 140... 
    end if;
 
    end if;
 
  end process action;
 
  end process action;
 
 
 
 
 
 
 
 
 
  -- comb logic
 
  -- comb logic
 
  transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_AM_FULL, i_X2U_EMPTY)
 
  transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL,
 
 
 
                        i_U2X_AM_FULL, i_X2U_EMPTY)
 
  begin  -- process transaction
 
  begin  -- process transaction
 
 
 
 
 
    -- default signal values to avoid latches:
 
    -- default signal values to avoid latches:
 
    s_FIFOrst       <= '0';
 
    s_FIFOrst       <= '0';
 
    s_bus_trans_dir <= readFromGPIF;
 
    s_bus_trans_dir <= readFromGPIF;
Line 202... Line 204... 
        -- in trans
 
        -- in trans
 
      when inRQ =>
 
      when inRQ =>
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX  <= '0';
 
        s_WRX  <= '0';
 
        s_RDYX <= '0';
 
        s_RDYX <= '0';
 
 
 
        s_U2X_WR_EN <= '0';
 
 
 
        o_RX        <= '0';
 
 
 
 
 
        -- state decisions
 
        -- state decisions
 
        if i_WRU = '1' and i_RDYU = '1' then
 
        if i_WRU = '1' and i_RDYU = '1' then
 
          nx_state <= rst;
 
          nx_state <= rst;
 
        elsif i_U2X_FULL = '0' then
 
        elsif i_U2X_FULL = '0' then
 
          nx_state <= inACK;
 
          nx_state <= inACK;
Line 215... Line 220... 
 
 
 
 
      when inACK =>
 
      when inACK =>
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
 
        s_U2X_WR_EN <= '1';
 
        s_U2X_WR_EN <= '0';
 
        o_RX        <= '1';
 
        o_RX        <= '1';
 
 
 
 
 
        -- state decisions
 
        -- state decisions
 
        if i_WRU = '1' and i_RDYU = '1' then
 
        if i_WRU = '1' and i_RDYU = '1' then
 
          nx_state <= rst;
 
          nx_state <= rst;
 
        elsif i_WRU = '1' then
 
        elsif i_WRU = '1' then
 
          nx_state <= inTrans;
 
          --nx_state <= inTrans;
 
          --nx_state <= inDummy;
 
          nx_state <= inWait;
 
        else
 
        else
 
          nx_state <= endInTrans;
 
          nx_state <= endInTrans;
 
        end if;
 
        end if;
 
 
 
 
 
 
 
        when inWait =>
 
 
 
        -- output signal values:
 
 
 
        s_WRX       <= '0';
 
 
 
        s_RDYX      <= '1';
 
 
 
        s_U2X_WR_EN <= '0';
 
 
 
        o_RX        <= '1';
 
 
 
 
 
 
 
        -- state decisions
 
 
 
        nx_state <= inTrans;
 
 
 
 
 
      when inTrans =>
 
      when inTrans =>
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
 
        s_U2X_WR_EN <= '1';
 
        s_U2X_WR_EN <= '1';
Line 257... Line 272... 
 
 
 
 
        -- state decisions
 
        -- state decisions
 
        if i_WRU = '1' and i_RDYU = '1' then
 
        if i_WRU = '1' and i_RDYU = '1' then
 
          nx_state <= rst;
 
          nx_state <= rst;
 
        elsif i_U2X_FULL = '0' then
 
        elsif i_U2X_FULL = '0' then
 
          --nx_state <= inThrotEnd;
 
          nx_state <= inThrotBreak;
 
          nx_state <= inACK;
 
          --nx_state <= inACK;
 
        elsif i_WRU = '0' then
 
        elsif i_WRU = '0' then
 
          nx_state <= endInTrans;
 
          nx_state <= endInTrans;
 
        else
 
        else
 
          nx_state <= inThrot;
 
          nx_state <= inThrot;
 
        end if;
 
        end if;
 
 
 
 
 
      --when inThrotEnd =>
 
      when inThrotBreak =>
 
 
 
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
 
 
 
 
 
 
        -- output signal values:
 
 
 
        s_WRX       <= '0';
 
 
 
        s_RDYX      <= '1';
 
 
 
        s_U2X_WR_EN <= '0';
 
 
 
        o_RX        <= '1';
 
 
 
 
 
 
 
        -- state decisions 
 
 
        --nx_state <= inThrotBreak2;
 
 
 
        nx_state <= inThrotEnd;
 
 
 
 
 
 
 
      --when inThrotBreak2 =>
 
      --  -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
      --  -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
 
 
 
 
      --  -- output signal values:
 
      --  -- output signal values:
 
      --  s_WRX       <= '0';
 
      --  s_WRX       <= '0';
 
      --  s_RDYX      <= '1';
 
      --  s_RDYX      <= '1';
 
      --  s_U2X_WR_EN <= '0';
 
      --  s_U2X_WR_EN <= '0';
 
      --  o_RX        <= '1';
 
      --  o_RX        <= '1';
 
 
 
 
 
      --  -- state decisions 
      --  -- state decisions 
      --  nx_state <= inACK;
 
      --  nx_state <= inThrotEnd;
 
 
 
 
 
 
 
      when inThrotEnd =>
 
 
 
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
 
 
 
 
 
 
        -- output signal values:
 
 
 
        s_WRX       <= '0';
 
 
 
        s_RDYX      <= '1';
 
 
 
        s_U2X_WR_EN <= '0';
 
 
 
        o_RX        <= '1';
 
 
 
 
 
 
 
        -- state decisions 
 
 
        nx_state <= inTrans;
 
 
 
 
 
      when endInTrans =>
 
      when endInTrans =>
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '0';
 
        s_RDYX      <= '0';
 
        s_U2X_WR_EN <= '1';
 
        s_U2X_WR_EN <= '0';
 
 
 
        o_RX        <= '0';
 
 
 
 
 
        -- state decisions
 
        -- state decisions
 
        nx_state <= idle;
 
        nx_state <= idle;
 
 
 
 
 
 
 
 

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