| Line 52... |
Line 52... |
port (
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port (
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i_nReset : in std_logic;
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i_nReset : in std_logic;
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i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock)
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i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock)
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i_WRU : in std_logic; -- write from GPIF
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i_WRU : in std_logic; -- write from GPIF
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i_RDYU : in std_logic; -- GPIF is ready
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i_RDYU : in std_logic; -- GPIF is ready
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i_EOM : in std_logic; -- all data for X2U transfer is in FIFO
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i_U2X_FULL : in std_logic;
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i_U2X_FULL : in std_logic;
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i_U2X_AM_FULL : in std_logic; -- signals for IN FIFO
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i_U2X_AM_FULL : in std_logic; -- signals for IN FIFO
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i_X2U_FULL_IFCLK : in std_logic;
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i_X2U_AM_EMPTY : in std_logic;
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i_X2U_AM_EMPTY : in std_logic;
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i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO
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i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO
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o_bus_trans_dir : out std_logic;
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o_bus_trans_dir : out std_logic;
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o_U2X_WR_EN : out std_logic; -- signals for IN FIFO
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o_U2X_WR_EN : out std_logic; -- signals for IN FIFO
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o_X2U_RD_EN : out std_logic; -- signals for OUT FIFO
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o_X2U_RD_EN : out std_logic; -- signals for OUT FIFO
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| Line 88... |
Line 90... |
signal s_bus_trans_dir : t_busAccess;
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signal s_bus_trans_dir : t_busAccess;
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type t_fsmState is (rst, idle, -- controll states
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type t_fsmState is (rst, idle, -- controll states
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inRQ, inACK, inWait, inTrans, inThrot,
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inRQ, inACK, inWait, inTrans, inThrot,
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inThrotBreak,inThrotBreak2, inThrotEnd, endInTrans, -- in com states
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inThrotBreak,inThrotBreak2, inThrotEnd,
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outRQ, outTrans, outWait, endOutTrans); -- out com states
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endInTrans, -- in com states
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outRQ, outTrans, outACK, outUSBwait, outFIFOwait,
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endOutTrans); -- out com states
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signal pr_state, nx_state : t_fsmState;
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signal pr_state, nx_state : t_fsmState;
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-- XST specific synthesize attributes
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-- XST specific synthesize attributes
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attribute safe_recovery_state of pr_state : signal is "idle";
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attribute safe_recovery_state of pr_state : signal is "idle";
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attribute safe_implementation of pr_state : signal is "yes";
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attribute safe_implementation of pr_state : signal is "yes";
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-- interconection signals
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-- interconection signals
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signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;
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signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;
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-- USB to Xilinx (U2X)
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-- USB to Xilinx (U2X)
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signal s_U2X_WR_EN : std_logic;
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signal s_U2X_WR_EN : std_logic;
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| Line 140... |
Line 145... |
end if;
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end if;
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end process action;
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end process action;
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-- comb logic
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-- comb logic
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transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL,
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transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
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i_U2X_AM_FULL, i_X2U_EMPTY)
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i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM)
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begin -- process transaction
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begin -- process transaction
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-- default signal values to avoid latches:
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-- default signal values to avoid latches:
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s_FIFOrst <= '0';
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s_FIFOrst <= '0';
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s_bus_trans_dir <= readFromGPIF;
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s_bus_trans_dir <= readFromGPIF;
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| Line 169... |
Line 174... |
s_U2X_WR_EN <= '0';
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s_U2X_WR_EN <= '0';
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s_X2U_RD_EN <= '0';
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s_X2U_RD_EN <= '0';
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s_ABORT <= '1';
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s_ABORT <= '1';
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o_RX <= '0';
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o_RX <= '0';
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o_TX <= '0';
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o_TX <= '0';
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s_bus_trans_dir <= readFromGPIF;
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s_bus_trans_dir <= readFromGPIF;
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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| Line 193... |
Line 197... |
-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_WRU = '1' and i_RDYU = '0' then
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elsif i_WRU = '1' and i_RDYU = '0' then
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nx_state <= inRQ;
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nx_state <= inRQ;
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elsif i_WRU = '0' and i_X2U_EMPTY = '0' then
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elsif i_WRU = '0' and
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(i_X2U_FULL_IFCLK = '1' or i_EOM = '1') and i_X2U_EMPTY = '0' then
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nx_state <= outRQ;
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nx_state <= outRQ;
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else
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else
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nx_state <= idle;
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nx_state <= idle;
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end if;
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end if;
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-----------------------------------------------------------------------
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-- in trans
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-- in trans
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when inRQ =>
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when inRQ =>
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-- output signal values:
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-- output signal values:
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s_WRX <= '0';
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s_WRX <= '0';
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s_RDYX <= '0';
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s_RDYX <= '0';
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| Line 255... |
Line 261... |
-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_WRU = '0' then
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elsif i_WRU = '0' then
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nx_state <= endInTrans;
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nx_state <= endInTrans;
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elsif i_U2X_FULL = '1' then
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elsif i_U2X_AM_FULL = '1' then
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nx_state <= inThrot;
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nx_state <= inThrot;
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else
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else
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nx_state <= inTrans;
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nx_state <= inTrans;
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end if;
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end if;
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| Line 271... |
Line 277... |
o_RX <= '1';
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o_RX <= '1';
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_U2X_FULL = '0' then
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elsif i_U2X_AM_FULL = '0' then
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nx_state <= inThrotBreak;
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nx_state <= inThrotBreak;
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--nx_state <= inACK;
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--nx_state <= inThrotEnd;
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elsif i_WRU = '0' then
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elsif i_WRU = '0' then
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nx_state <= endInTrans;
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nx_state <= endInTrans;
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else
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else
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nx_state <= inThrot;
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nx_state <= inThrot;
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end if;
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end if;
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| Line 327... |
Line 333... |
o_RX <= '0';
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o_RX <= '0';
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-- state decisions
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-- state decisions
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nx_state <= idle;
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nx_state <= idle;
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-----------------------------------------------------------------------
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-- out trans
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-- out trans
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when outRQ =>
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when outRQ =>
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-- output signal values:
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-- output signal values:
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s_WRX <= '1';
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s_WRX <= '1';
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s_RDYX <= '0';
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s_RDYX <= '0';
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s_X2U_RD_EN <= '0';
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_WRU = '1' and i_RDYU = '0' then
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elsif i_WRU = '1' and i_RDYU = '0' then
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nx_state <= inRQ;
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nx_state <= inRQ;
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elsif i_WRU = '0' and i_RDYU = '0' then -- vervollständigt, wenn ez-usb noch beschäfigt mit altem transfer
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--s_X2U_RD_EN <= '1';
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nx_state <= outTrans;
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-- s_bus_trans_dir <= writeToGPIF;
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else
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else
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nx_state <= outRQ;
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nx_state <= outACK;
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end if;
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end if;
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when outACK =>
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-- output signal values:
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s_WRX <= '1';
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s_RDYX <= '0';
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s_X2U_RD_EN <= '1';
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o_TX <= '1';
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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elsif i_WRU = '0' and i_RDYU = '1' then
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nx_state <= outTrans;
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else
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nx_state <= outUSBwait;
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end if;
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when outTrans =>
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when outTrans =>
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-- output signal values:
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-- output signal values:
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s_WRX <= '1';
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s_WRX <= '1';
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s_RDYX <= '0';
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s_RDYX <= '0';
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s_X2U_RD_EN <= '1';
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s_X2U_RD_EN <= '1';
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s_bus_trans_dir <= writeToGPIF;
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o_TX <= '1';
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o_TX <= '1';
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s_bus_trans_dir <= writeToGPIF;
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_X2U_EMPTY = '1' then
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elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
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nx_state <= endOutTrans;
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nx_state <= endOutTrans;
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elsif i_X2U_EMPTY = '1' and i_EOM = '0' then
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nx_state <= outFIFOwait;
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elsif i_WRU = '0' and i_RDYU = '1' then
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elsif i_WRU = '0' and i_RDYU = '1' then
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nx_state <= outTrans;
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nx_state <= outTrans;
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else
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else
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--s_X2U_RD_EN <= '0'; -- to realise a wait case
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nx_state <= outUSBwait;
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nx_state <= outWait;
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end if;
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end if;
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when outWait =>
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when outUSBwait =>
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-- output signal values:
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-- output signal values:
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s_WRX <= '1';
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s_WRX <= '1';
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s_RDYX <= '0';
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s_RDYX <= '0';
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s_X2U_RD_EN <= '0';
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s_X2U_RD_EN <= '0';
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o_TX <= '1';
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o_TX <= '1';
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| Line 382... |
Line 401... |
if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_WRU = '0' and i_RDYU = '1' then
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elsif i_WRU = '0' and i_RDYU = '1' then
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nx_state <= outTrans;
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nx_state <= outTrans;
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else
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else
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nx_state <= outWait;
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nx_state <= outUSBwait;
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end if;
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when outFIFOwait =>
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-- output signal values:
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s_WRX <= '1';
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s_RDYX <= '1';
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s_X2U_RD_EN <= '0';
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o_TX <= '1';
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s_bus_trans_dir <= writeToGPIF;
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
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nx_state <= endOutTrans;
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elsif i_X2U_EMPTY = '0' and i_EOM = '0' then
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nx_state <= outTrans;
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else
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nx_state <= outFIFOwait;
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end if;
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end if;
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when endOutTrans =>
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when endOutTrans =>
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-- output signal values:
|
-- output signal values:
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s_RDYX <= '0';
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s_RDYX <= '0';
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s_WRX <= '1'; -- nötig um letzte 16bit an ez-usb zu schreiben
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s_WRX <= '0';
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s_X2U_RD_EN <= '1'; -- nötig da empyte flag schon beim ersten fifo zugriff auftaucht, zweite 16bit müssen noch gelesen werden
|
s_X2U_RD_EN <= '0';
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s_bus_trans_dir <= writeToGPIF;
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s_bus_trans_dir <= writeToGPIF;
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|
-- state decisions
|
-- state decisions
|
|
if i_RDYU = '0' then
|
nx_state <= idle;
|
nx_state <= idle;
|
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else
|
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nx_state <= endOutTrans;
|
|
end if;
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|
-- error case
|
-- error case
|
when others =>
|
when others =>
|
nx_state <= idle;
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nx_state <= idle;
|
end case;
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end case;
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