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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [gpif_com_fsm.vhd] - Diff between revs 20 and 21

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Rev 20 Rev 21
Line 147... Line 147... 
 
 
 
 
 
 
 
 
  -- comb logic
 
  -- comb logic
 
  transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
 
  transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
 
                        i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM)
 
                        i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM)
 
 
 
    variable state_number : std_logic_vector(3 downto 0);  -- debug information
 
  begin  -- process transaction
 
  begin  -- process transaction
 
 
 
 
 
    -- default signal values to avoid latches:
 
    -- default signal values to avoid latches:
 
    s_FIFOrst       <= '0';
 
    s_FIFOrst       <= '0';
 
    s_bus_trans_dir <= readFromGPIF;
 
    s_bus_trans_dir <= readFromGPIF;
Line 165... Line 166... 
 
 
 
 
    case pr_state is
 
    case pr_state is
 
      -- controll
 
      -- controll
 
 
 
 
 
      when rst =>
 
      when rst =>
 
 
 
        state_number := x"1";
 
        -- output signal values:
 
        -- output signal values:
 
        s_FIFOrst   <= '1';
 
        s_FIFOrst   <= '1';
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '0';
 
        s_RDYX      <= '0';
 
        s_U2X_WR_EN <= '0';
 
        s_U2X_WR_EN <= '0';
Line 184... Line 186... 
        else
 
        else
 
          nx_state <= idle;
 
          nx_state <= idle;
 
        end if;
 
        end if;
 
 
 
 
 
      when idle =>
 
      when idle =>
 
 
 
        state_number := x"2";
 
        -- output signal values:
 
        -- output signal values:
 
        s_FIFOrst       <= '0';
 
        s_FIFOrst       <= '0';
 
        s_WRX           <= '0';
 
        s_WRX           <= '0';
 
        s_RDYX          <= '0';
 
        s_RDYX          <= '0';
 
        s_U2X_WR_EN     <= '0';
 
        s_U2X_WR_EN     <= '0';
Line 207... Line 210... 
        end if;
 
        end if;
 
 
 
 
 
        -----------------------------------------------------------------------
 
        -----------------------------------------------------------------------
 
        -- in trans
 
        -- in trans
 
      when inRQ =>
 
      when inRQ =>
 
 
 
        state_number := x"3";
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX  <= '0';
 
        s_WRX  <= '0';
 
        s_RDYX <= '0';
 
        s_RDYX <= '0';
 
        s_U2X_WR_EN <= '0';
 
        s_U2X_WR_EN <= '0';
 
        o_RX        <= '0';
 
        o_RX        <= '0';
Line 223... Line 227... 
        else
 
        else
 
          nx_state <= idle;
 
          nx_state <= idle;
 
        end if;
 
        end if;
 
 
 
 
 
      when inACK =>
 
      when inACK =>
 
 
 
        state_number := x"4";
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
 
        s_U2X_WR_EN <= '0';
 
        s_U2X_WR_EN <= '0';
 
        o_RX        <= '1';
 
        o_RX        <= '1';
Line 240... Line 245... 
        else
 
        else
 
          nx_state <= endInTrans;
 
          nx_state <= endInTrans;
 
        end if;
 
        end if;
 
 
 
 
 
        when inWait =>
 
        when inWait =>
 
 
 
        state_number := x"5";
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
 
        s_U2X_WR_EN <= '0';
 
        s_U2X_WR_EN <= '0';
 
        o_RX        <= '1';
 
        o_RX        <= '1';
 
 
 
 
 
        -- state decisions
 
        -- state decisions
 
        nx_state <= inTrans;
 
        nx_state <= inTrans;
 
 
 
 
 
      when inTrans =>
 
      when inTrans =>
 
 
 
        state_number := x"6";
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
 
        s_U2X_WR_EN <= '1';
 
        s_U2X_WR_EN <= '1';
 
        o_RX        <= '1';
 
        o_RX        <= '1';
Line 268... Line 275... 
        else
 
        else
 
          nx_state <= inTrans;
 
          nx_state <= inTrans;
 
        end if;
 
        end if;
 
 
 
 
 
      when inThrot =>
 
      when inThrot =>
 
 
 
        state_number := x"7";
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '0';
 
        s_RDYX      <= '0';
 
        s_U2X_WR_EN <= '0';
 
        s_U2X_WR_EN <= '0';
 
        o_RX        <= '1';
 
        o_RX        <= '1';
Line 287... Line 295... 
        else
 
        else
 
          nx_state <= inThrot;
 
          nx_state <= inThrot;
 
        end if;
 
        end if;
 
 
 
 
 
      when inThrotBreak =>
 
      when inThrotBreak =>
 
 
 
        state_number := x"8";
 
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
 
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
Line 312... Line 321... 
 
 
 
 
      --  -- state decisions 
      --  -- state decisions 
      --  nx_state <= inThrotEnd;
 
      --  nx_state <= inThrotEnd;
 
 
 
 
 
      when inThrotEnd =>
 
      when inThrotEnd =>
 
 
 
        state_number := x"9";
 
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
 
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
Line 324... Line 334... 
 
 
 
 
        -- state decisions 
        -- state decisions 
        nx_state <= inTrans;
 
        nx_state <= inTrans;
 
 
 
 
 
      when endInTrans =>
 
      when endInTrans =>
 
 
 
        state_number := x"A";
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '0';
 
        s_RDYX      <= '0';
 
        s_U2X_WR_EN <= '0';
 
        s_U2X_WR_EN <= '0';
 
        o_RX        <= '0';
 
        o_RX        <= '0';
Line 336... Line 347... 
        nx_state <= idle;
 
        nx_state <= idle;
 
 
 
 
 
        -----------------------------------------------------------------------
 
        -----------------------------------------------------------------------
 
        -- out trans
 
        -- out trans
 
      when outRQ =>
 
      when outRQ =>
 
 
 
        state_number := x"B";
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '1';
 
        s_WRX       <= '1';
 
        s_RDYX      <= '0';
 
        s_RDYX      <= '0';
 
        s_X2U_RD_EN <= '0';
 
        s_X2U_RD_EN <= '0';
 
 
 
 
Line 351... Line 363... 
        else
 
        else
 
          nx_state <= outACK;
 
          nx_state <= outACK;
 
        end if;
 
        end if;
 
 
 
 
 
     when outACK =>
 
     when outACK =>
 
 
 
        state_number := x"C";
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '1';
 
        s_WRX       <= '1';
 
        s_RDYX      <= '0';
 
        s_RDYX      <= '0';
 
        s_X2U_RD_EN <= '1';
 
        s_X2U_RD_EN <= '1';
 
        o_TX        <= '1';
 
        o_TX        <= '1';
Line 367... Line 380... 
        else
 
        else
 
          nx_state <= outUSBwait;
 
          nx_state <= outUSBwait;
 
        end if;
 
        end if;
 
 
 
 
 
      when outTrans =>
 
      when outTrans =>
 
 
 
        state_number := x"D";
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX           <= '1';
 
        s_WRX           <= '1';
 
        s_RDYX          <= '0';
 
        s_RDYX          <= '0';
 
        s_X2U_RD_EN     <= '1';
 
        s_X2U_RD_EN     <= '1';
 
        o_TX            <= '1';
 
        o_TX            <= '1';
Line 388... Line 402... 
        else
 
        else
 
          nx_state    <= outUSBwait;
 
          nx_state    <= outUSBwait;
 
        end if;
 
        end if;
 
 
 
 
 
      when outUSBwait =>
 
      when outUSBwait =>
 
 
 
        state_number := x"E";
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '1';
 
        s_WRX       <= '1';
 
        s_RDYX      <= '0';
 
        s_RDYX      <= '0';
 
        s_X2U_RD_EN <= '0';
 
        s_X2U_RD_EN <= '0';
 
        o_TX        <= '1';
 
        o_TX        <= '1';
Line 405... Line 420... 
        else
 
        else
 
          nx_state <= outUSBwait;
 
          nx_state <= outUSBwait;
 
        end if;
 
        end if;
 
 
 
 
 
      when outFIFOwait =>
 
      when outFIFOwait =>
 
 
 
        state_number := x"F";
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '1';
 
        s_WRX       <= '1';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
 
        s_X2U_RD_EN <= '0';
 
        s_X2U_RD_EN <= '0';
 
        o_TX        <= '1';
 
        o_TX        <= '1';
Line 424... Line 440... 
        else
 
        else
 
          nx_state <= outFIFOwait;
 
          nx_state <= outFIFOwait;
 
        end if;
 
        end if;
 
 
 
 
 
      when endOutTrans =>
 
      when endOutTrans =>
 
 
 
        state_number := x"9";
 
        -- output signal values:
 
        -- output signal values:
 
        s_RDYX          <= '0';
 
        s_RDYX          <= '0';
 
        s_WRX           <= '0';
 
        s_WRX           <= '0';
 
        s_X2U_RD_EN     <= '0';
 
        s_X2U_RD_EN     <= '0';
 
        s_bus_trans_dir <= writeToGPIF;
 
        s_bus_trans_dir <= writeToGPIF;

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