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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [gpif_com_fsm.vhd] - Diff between revs 27 and 28

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Rev 27 Rev 28
Line 89... Line 89... 
  type   t_busAccess is (readFromGPIF, writeToGPIF);
 
  type   t_busAccess is (readFromGPIF, writeToGPIF);
 
  signal s_bus_trans_dir : t_busAccess;
 
  signal s_bus_trans_dir : t_busAccess;
 
 
 
 
 
 
 
 
 
  type t_fsmState is (rst, idle,        -- controll states
 
  type t_fsmState is (rst, idle,        -- controll states
 
 
 
                      -- in com states
 
                      inRQ, inACK, inWait, inTrans, inThrot,
 
                      inRQ, inACK, inWait, inTrans, inThrot,
 
                      inThrotBreak,inThrotBreak2, inThrotEnd,
 
                      inThrotBreak, inThrotEnd,
 
                      endInTrans,  -- in com states
 
                      endInTrans,
 
                      outRQ, outRQdelay, outTrans, outACK, outUSBwait,
 
                      -- out com states
 
                      outFIFOwait, endOutTrans);  -- out com states
 
                      outRQ, outRQdelay, outTrans, outACK, outACKwait,
 
 
 
                      outUSBwait, outUSBwaitEnd, outFIFOwait, endOutTrans);
 
 
 
 
 
 
 
 
 
 
 
 
 
  signal pr_state, nx_state : t_fsmState;
 
  signal pr_state, nx_state : t_fsmState;
 
  -- XST specific synthesize attributes
 
  -- XST specific synthesize attributes
Line 145... Line 147... 
 
 
 
 
 
 
 
 
  -- comb logic
 
  -- comb logic
 
  transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
 
  transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
 
                        i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM)
 
                        i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM)
 
    variable state_number : std_logic_vector(3 downto 0);  -- debug information
 
 
 
  begin  -- process transaction
 
  begin  -- process transaction
 
 
 
 
 
    -- default signal values to avoid latches:
 
    -- default signal values to avoid latches:
 
    s_FIFOrst       <= '0';
 
    s_FIFOrst       <= '0';
 
    s_bus_trans_dir <= readFromGPIF;
 
    s_bus_trans_dir <= readFromGPIF;
Line 164... Line 165... 
 
 
 
 
    case pr_state is
 
    case pr_state is
 
      -- controll
 
      -- controll
 
 
 
 
 
      when rst =>
 
      when rst =>
 
        state_number := x"1";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_FIFOrst   <= '1';
 
        s_FIFOrst   <= '1';
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '0';
 
        s_RDYX      <= '0';
 
        s_U2X_WR_EN <= '0';
 
        s_U2X_WR_EN <= '0';
Line 184... Line 184... 
        else
 
        else
 
          nx_state <= idle;
 
          nx_state <= idle;
 
        end if;
 
        end if;
 
 
 
 
 
      when idle =>
 
      when idle =>
 
        state_number := x"2";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_FIFOrst       <= '0';
 
        s_FIFOrst       <= '0';
 
        s_WRX           <= '0';
 
        s_WRX           <= '0';
 
        s_RDYX          <= '0';
 
        s_RDYX          <= '0';
 
        s_U2X_WR_EN     <= '0';
 
        s_U2X_WR_EN     <= '0';
Line 208... Line 207... 
        end if;
 
        end if;
 
 
 
 
 
        -----------------------------------------------------------------------
 
        -----------------------------------------------------------------------
 
        -- in trans
 
        -- in trans
 
      when inRQ =>
 
      when inRQ =>
 
        state_number := x"3";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX  <= '0';
 
        s_WRX  <= '0';
 
        s_RDYX <= '0';
 
        s_RDYX <= '0';
 
        s_U2X_WR_EN <= '0';
 
        s_U2X_WR_EN <= '0';
 
        o_RX        <= '0';
 
        o_RX        <= '0';
Line 225... Line 223... 
        else
 
        else
 
          nx_state <= idle;
 
          nx_state <= idle;
 
        end if;
 
        end if;
 
 
 
 
 
      when inACK =>
 
      when inACK =>
 
        state_number := x"4";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
 
        s_U2X_WR_EN <= '0';
 
        s_U2X_WR_EN <= '0';
 
        o_RX        <= '1';
 
        o_RX        <= '1';
 
 
 
 
 
        -- state decisions
 
        -- state decisions
 
        if i_WRU = '1' and i_RDYU = '1' then
 
        if i_WRU = '1' and i_RDYU = '1' then
 
          nx_state <= rst;
 
          nx_state <= rst;
 
        elsif i_WRU = '1' then
 
        elsif i_WRU = '1' then
 
          --nx_state <= inTrans;
 
 
 
          nx_state <= inWait;
 
          nx_state <= inWait;
 
        else
 
        else
 
          nx_state <= endInTrans;
 
          nx_state <= endInTrans;
 
        end if;
 
        end if;
 
 
 
 
 
        when inWait =>
 
        when inWait =>
 
        state_number := x"5";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
 
        s_U2X_WR_EN <= '0';
 
        s_U2X_WR_EN <= '0';
 
        o_RX        <= '1';
 
        o_RX        <= '1';
 
 
 
 
 
        -- state decisions
 
        -- state decisions
 
        nx_state <= inTrans;
 
        nx_state <= inTrans;
 
 
 
 
 
      when inTrans =>
 
      when inTrans =>
 
        state_number := x"6";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
 
        s_U2X_WR_EN <= '1';
 
        s_U2X_WR_EN <= '1';
 
        o_RX        <= '1';
 
        o_RX        <= '1';
Line 273... Line 267... 
        else
 
        else
 
          nx_state <= inTrans;
 
          nx_state <= inTrans;
 
        end if;
 
        end if;
 
 
 
 
 
      when inThrot =>
 
      when inThrot =>
 
        state_number := x"7";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '0';
 
        s_RDYX      <= '0';
 
        s_U2X_WR_EN <= '0';
 
        s_U2X_WR_EN <= '0';
 
        o_RX        <= '1';
 
        o_RX        <= '1';
Line 293... Line 286... 
        else
 
        else
 
          nx_state <= inThrot;
 
          nx_state <= inThrot;
 
        end if;
 
        end if;
 
 
 
 
 
      when inThrotBreak =>
 
      when inThrotBreak =>
 
        state_number := x"8";
 
 
 
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
 
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
 
        s_U2X_WR_EN <= '0';
 
        s_U2X_WR_EN <= '0';
 
        o_RX        <= '1';
 
        o_RX        <= '1';
 
 
 
 
 
        -- state decisions 
        -- state decisions 
        --nx_state <= inThrotBreak2;
 
 
 
        nx_state <= inThrotEnd;
 
        nx_state <= inThrotEnd;
 
 
 
 
 
      --when inThrotBreak2 =>
 
 
 
      --  -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
 
 
 
 
 
 
      --  -- output signal values:
 
 
 
      --  s_WRX       <= '0';
 
 
 
      --  s_RDYX      <= '1';
 
 
 
      --  s_U2X_WR_EN <= '0';
 
 
 
      --  o_RX        <= '1';
 
 
 
 
 
 
 
      --  -- state decisions 
 
 
      --  nx_state <= inThrotEnd;
 
 
 
 
 
 
 
      when inThrotEnd =>
 
      when inThrotEnd =>
 
        state_number := x"9";
 
 
 
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
        -- this is a one clock delay to help the fx2 to see the RDYX signal.
 
 
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
Line 332... Line 310... 
 
 
 
 
        -- state decisions 
        -- state decisions 
        nx_state <= inTrans;
 
        nx_state <= inTrans;
 
 
 
 
 
      when endInTrans =>
 
      when endInTrans =>
 
        state_number := x"A";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '0';
 
        s_WRX       <= '0';
 
        s_RDYX      <= '0';
 
        s_RDYX      <= '0';
 
        s_U2X_WR_EN <= '0';
 
        s_U2X_WR_EN <= '0';
 
        o_RX        <= '0';
 
        o_RX        <= '0';
Line 345... Line 322... 
        nx_state <= idle;
 
        nx_state <= idle;
 
 
 
 
 
        -----------------------------------------------------------------------
 
        -----------------------------------------------------------------------
 
        -- out trans
 
        -- out trans
 
      when outRQ =>
 
      when outRQ =>
 
        state_number := x"B";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '1';
 
        s_WRX       <= '1';
 
        s_RDYX      <= '0';
 
        s_RDYX      <= '0';
 
        s_X2U_RD_EN <= '0';
 
        s_X2U_RD_EN <= '0';
 
 
 
 
Line 376... Line 352... 
        else
 
        else
 
          nx_state <= outACK;
 
          nx_state <= outACK;
 
        end if;
 
        end if;
 
 
 
 
 
     when outACK =>
 
     when outACK =>
 
        state_number := x"C";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '1';
 
        s_WRX       <= '1';
 
        s_RDYX      <= '0';
 
        s_RDYX      <= '0';
 
        s_X2U_RD_EN <= '1';
 
        s_X2U_RD_EN <= '1';
 
        o_TX        <= '1';
 
        o_TX        <= '1';
Line 389... Line 364... 
        if i_WRU = '1' and i_RDYU = '1' then
 
        if i_WRU = '1' and i_RDYU = '1' then
 
          nx_state <= rst;
 
          nx_state <= rst;
 
        elsif i_WRU = '0' and i_RDYU = '1' then
 
        elsif i_WRU = '0' and i_RDYU = '1' then
 
          nx_state <= outTrans;
 
          nx_state <= outTrans;
 
        else
 
        else
 
          nx_state <= outUSBwait;
 
          nx_state <= outACKwait;
 
 
 
        end if;
 
 
 
 
 
 
 
      when outACKwait =>
 
 
 
        -- output signal values:
 
 
 
        s_WRX       <= '1';
 
 
 
        s_RDYX      <= '0';
 
 
 
        s_X2U_RD_EN <= '0';
 
 
 
        o_TX        <= '1';
 
 
 
 
 
 
 
        -- state decisions
 
 
 
        if i_WRU = '1' and i_RDYU = '1' then
 
 
 
          nx_state <= rst;
 
 
 
        elsif i_WRU = '0' and i_RDYU = '1' then
 
 
 
          nx_state <= outTrans;
 
 
 
        else
 
 
 
          nx_state <= outACKwait;
 
        end if;
 
        end if;
 
 
 
 
 
      when outTrans =>
 
      when outTrans =>
 
        state_number := x"D";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX           <= '1';
 
        s_WRX           <= '1';
 
        s_RDYX          <= '0';
 
        s_RDYX          <= '0';
 
        s_X2U_RD_EN     <= '1';
 
        s_X2U_RD_EN     <= '1';
 
        o_TX            <= '1';
 
        o_TX            <= '1';
Line 415... Line 405... 
        else
 
        else
 
          nx_state    <= outUSBwait;
 
          nx_state    <= outUSBwait;
 
        end if;
 
        end if;
 
 
 
 
 
      when outUSBwait =>
 
      when outUSBwait =>
 
        state_number := x"E";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '1';
 
        s_WRX       <= '1';
 
        s_RDYX      <= '0';
 
        s_RDYX      <= '0';
 
        s_X2U_RD_EN <= '0';
 
        s_X2U_RD_EN <= '0';
 
        o_TX        <= '1';
 
        o_TX        <= '1';
Line 429... Line 418... 
        if i_WRU = '1' and i_RDYU = '1' then
 
        if i_WRU = '1' and i_RDYU = '1' then
 
          nx_state <= rst;
 
          nx_state <= rst;
 
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
 
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
 
          nx_state <= endOutTrans;
 
          nx_state <= endOutTrans;
 
        elsif i_WRU = '0' and i_RDYU = '1' then
 
        elsif i_WRU = '0' and i_RDYU = '1' then
 
          nx_state <= outTrans;
 
          nx_state <= outUSBwaitEnd;
 
        else
 
        else
 
          nx_state <= outUSBwait;
 
          nx_state <= outUSBwait;
 
        end if;
 
        end if;
 
 
 
 
 
 
 
      when outUSBwaitEnd =>
 
 
 
        -- output signal values:
 
 
 
        s_WRX       <= '1';
 
 
 
        s_RDYX      <= '1';
 
 
 
        s_X2U_RD_EN <= '0';
 
 
 
        o_TX        <= '1';
 
 
 
        s_bus_trans_dir <= writeToGPIF;
 
 
 
 
 
 
 
        -- state decisions
 
 
 
        nx_state <= outTrans;
 
 
 
 
 
      when outFIFOwait =>
 
      when outFIFOwait =>
 
        state_number := x"F";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_WRX       <= '1';
 
        s_WRX       <= '1';
 
        s_RDYX      <= '1';
 
        s_RDYX      <= '1';
 
        s_X2U_RD_EN <= '0';
 
        s_X2U_RD_EN <= '0';
 
        o_TX        <= '1';
 
        o_TX        <= '1';
Line 455... Line 454... 
        else
 
        else
 
          nx_state <= outFIFOwait;
 
          nx_state <= outFIFOwait;
 
        end if;
 
        end if;
 
 
 
 
 
      when endOutTrans =>
 
      when endOutTrans =>
 
        state_number := x"9";
 
 
 
        -- output signal values:
 
        -- output signal values:
 
        s_RDYX          <= '0';
 
        s_RDYX          <= '0';
 
        s_WRX           <= '0';
 
        s_WRX           <= '0';
 
        s_X2U_RD_EN     <= '0';
 
        s_X2U_RD_EN     <= '0';
 
        s_bus_trans_dir <= writeToGPIF;
 
        s_bus_trans_dir <= writeToGPIF;

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