| Line 49... |
Line 49... |
use work.GECKO3COM_defines.all;
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use work.GECKO3COM_defines.all;
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entity gpif_com_fsm is
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entity gpif_com_fsm is
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port (
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port (
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i_nReset : in std_logic;
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i_nReset : in std_logic;
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i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock)
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i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and
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-- provides the clock)
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i_WRU : in std_logic; -- write from GPIF
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i_WRU : in std_logic; -- write from GPIF
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i_RDYU : in std_logic; -- GPIF is ready
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i_RDYU : in std_logic; -- GPIF is ready
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i_EOM : in std_logic; -- all data for X2U transfer is in FIFO
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i_EOM : in std_logic; -- all data for X2U transfer is in FIFO
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i_U2X_FULL : in std_logic;
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i_U2X_FULL : in std_logic;
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i_U2X_AM_FULL : in std_logic; -- signals for IN FIFO
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i_U2X_AM_FULL : in std_logic; -- signals for IN FIFO
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i_X2U_FULL_IFCLK : in std_logic;
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i_X2U_AM_EMPTY : in std_logic;
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i_X2U_AM_EMPTY : in std_logic;
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i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO
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i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO
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o_dbus_out_mux_sel : out std_logic;
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o_bus_trans_dir : out std_logic;
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o_bus_trans_dir : out std_logic;
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o_U2X_WR_EN : out std_logic; -- signals for IN FIFO
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o_U2X_WR_EN : out std_logic; -- signals for IN FIFO
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o_X2U_RD_EN : out std_logic; -- signals for OUT FIFO
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o_X2U_RD_EN : out std_logic; -- signals for OUT FIFO
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o_FIFOrst : out std_logic;
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o_FIFOrst : out std_logic;
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o_WRX : out std_logic; -- To write to GPIF
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o_WRX : out std_logic; -- To write to GPIF
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o_RDYX : out std_logic; -- Core is ready
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o_RDYX : out std_logic; -- Core is ready
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o_ABORT : out std_logic; -- abort condition detected. we have to flush the data
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o_ABORT : out std_logic; -- abort condition detected.
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-- we have to flush the data
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o_RX : out std_logic;
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o_RX : out std_logic;
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o_TX : out std_logic --
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o_TX : out std_logic --
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);
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);
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end gpif_com_fsm;
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end gpif_com_fsm;
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| Line 95... |
Line 97... |
inRQ, inACK, inWait, inTrans, inThrot,
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inRQ, inACK, inWait, inTrans, inThrot,
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inThrotBreak, inThrotEnd,
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inThrotBreak, inThrotEnd,
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endInTrans,
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endInTrans,
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-- out com states
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-- out com states
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outRQ, outRQdelay, outTrans, outACK, outACKwait,
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outRQ, outRQdelay, outTrans, outACK, outACKwait,
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outUSBwait, outUSBwaitEnd, outFIFOwait, endOutTrans);
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outUSBwait, outFIFOwait, endOutTrans);
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signal pr_state, nx_state : t_fsmState;
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signal pr_state, nx_state : t_fsmState;
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-- XST specific synthesize attributes
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-- XST specific synthesize attributes
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| Line 113... |
Line 115... |
-- USB to Xilinx (U2X)
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-- USB to Xilinx (U2X)
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signal s_U2X_WR_EN : std_logic;
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signal s_U2X_WR_EN : std_logic;
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-- Xilinx to USB (X2U)
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-- Xilinx to USB (X2U)
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signal s_X2U_RD_EN : std_logic;
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signal s_X2U_RD_EN : std_logic;
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signal s_dbus_out_mux_sel : std_logic;
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begin
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begin
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| Line 125... |
Line 128... |
o_WRX <= s_WRX;
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o_WRX <= s_WRX;
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o_RDYX <= s_RDYX;
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o_RDYX <= s_RDYX;
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o_U2X_WR_EN <= s_U2X_WR_EN;
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o_U2X_WR_EN <= s_U2X_WR_EN;
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o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';
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o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';
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o_ABORT <= s_ABORT;
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o_ABORT <= s_ABORT;
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o_dbus_out_mux_sel <= s_dbus_out_mux_sel;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- FSM GPIF
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-- FSM GPIF
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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| Line 146... |
Line 150... |
end process action;
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end process action;
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-- comb logic
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-- comb logic
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transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
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transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
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i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM)
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i_X2U_EMPTY, i_EOM)
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begin -- process transaction
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begin -- process transaction
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-- default signal values to avoid latches:
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-- default signal values to avoid latches:
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s_FIFOrst <= '0';
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s_FIFOrst <= '0';
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s_bus_trans_dir <= readFromGPIF;
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s_bus_trans_dir <= readFromGPIF;
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s_U2X_WR_EN <= '0';
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s_U2X_WR_EN <= '0';
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s_X2U_RD_EN <= '0';
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s_X2U_RD_EN <= '0';
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s_dbus_out_mux_sel <= '0';
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nx_state <= idle;
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nx_state <= idle;
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s_WRX <= '0';
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s_WRX <= '0';
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s_RDYX <= '0';
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s_RDYX <= '0';
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s_ABORT <= '0';
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s_ABORT <= '0';
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o_RX <= '0';
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o_RX <= '0';
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| Line 172... |
Line 177... |
s_WRX <= '0';
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s_WRX <= '0';
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s_RDYX <= '0';
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s_RDYX <= '0';
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s_U2X_WR_EN <= '0';
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s_U2X_WR_EN <= '0';
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s_X2U_RD_EN <= '0';
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s_X2U_RD_EN <= '0';
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s_ABORT <= '1';
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s_ABORT <= '1';
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s_dbus_out_mux_sel <= '0';
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o_RX <= '0';
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o_RX <= '0';
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o_TX <= '0';
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o_TX <= '0';
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s_bus_trans_dir <= readFromGPIF;
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s_bus_trans_dir <= readFromGPIF;
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-- state decisions
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-- state decisions
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| Line 198... |
Line 204... |
if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_WRU = '1' and i_RDYU = '0' then
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elsif i_WRU = '1' and i_RDYU = '0' then
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nx_state <= inRQ;
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nx_state <= inRQ;
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elsif i_WRU = '0' and
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elsif i_WRU = '0' and
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--(i_X2U_FULL_IFCLK = '1' or i_EOM = '1') and i_X2U_EMPTY = '0' then
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i_X2U_EMPTY = '0' then
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i_X2U_EMPTY = '0' then
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nx_state <= outRQ;
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nx_state <= outRQ;
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else
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else
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nx_state <= idle;
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nx_state <= idle;
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end if;
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end if;
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Line 385... |
-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_WRU = '0' and i_RDYU = '1' then
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elsif i_WRU = '0' and i_RDYU = '1' then
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nx_state <= outTrans;
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nx_state <= outTrans;
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s_X2U_RD_EN <= '1';
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else
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else
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nx_state <= outACKwait;
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nx_state <= outACKwait;
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end if;
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end if;
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when outTrans =>
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when outTrans =>
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| Line 392... |
Line 396... |
s_WRX <= '1';
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s_WRX <= '1';
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s_RDYX <= '0';
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s_RDYX <= '0';
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s_X2U_RD_EN <= '1';
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s_X2U_RD_EN <= '1';
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o_TX <= '1';
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o_TX <= '1';
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s_bus_trans_dir <= writeToGPIF;
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s_bus_trans_dir <= writeToGPIF;
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s_dbus_out_mux_sel <= '0';
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
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elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
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| Line 414... |
Line 419... |
s_WRX <= '1';
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s_WRX <= '1';
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s_RDYX <= '0';
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s_RDYX <= '0';
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s_X2U_RD_EN <= '0';
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s_X2U_RD_EN <= '0';
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o_TX <= '1';
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o_TX <= '1';
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s_bus_trans_dir <= writeToGPIF;
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s_bus_trans_dir <= writeToGPIF;
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s_dbus_out_mux_sel <= '1';
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
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elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
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nx_state <= endOutTrans;
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nx_state <= endOutTrans;
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elsif i_WRU = '0' and i_RDYU = '1' then
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elsif i_WRU = '0' and i_RDYU = '1' then
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nx_state <= outUSBwaitEnd;
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nx_state <= outTrans;
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else
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else
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nx_state <= outUSBwait;
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nx_state <= outUSBwait;
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end if;
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end if;
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when outUSBwaitEnd =>
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-- output signal values:
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s_WRX <= '1';
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s_RDYX <= '0';
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s_X2U_RD_EN <= '1';
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o_TX <= '1';
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s_bus_trans_dir <= writeToGPIF;
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-- state decisions
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nx_state <= outTrans;
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when outFIFOwait =>
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when outFIFOwait =>
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-- output signal values:
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-- output signal values:
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s_WRX <= '1';
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s_WRX <= '1';
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s_RDYX <= '1';
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s_RDYX <= '1';
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s_X2U_RD_EN <= '0';
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s_X2U_RD_EN <= '0';
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| Line 452... |
Line 447... |
nx_state <= rst;
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nx_state <= rst;
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elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
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elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
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nx_state <= endOutTrans;
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nx_state <= endOutTrans;
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elsif i_X2U_EMPTY = '0' then
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elsif i_X2U_EMPTY = '0' then
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nx_state <= outTrans;
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nx_state <= outTrans;
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s_X2U_RD_EN <= '1';
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else
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else
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nx_state <= outFIFOwait;
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nx_state <= outFIFOwait;
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end if;
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end if;
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when endOutTrans =>
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when endOutTrans =>
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