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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [gpif_com_fsm.vhd] - Diff between revs 29 and 30

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Rev 29 Rev 30
Line 49... Line 49...
use work.GECKO3COM_defines.all;
use work.GECKO3COM_defines.all;
 
 
entity gpif_com_fsm is
entity gpif_com_fsm is
  port (
  port (
    i_nReset         : in  std_logic;
    i_nReset         : in  std_logic;
    i_IFCLK          : in  std_logic;  -- GPIF CLK (GPIF is Master and provides the clock)
    i_IFCLK            : in  std_logic;  -- GPIF CLK (GPIF is Master and
 
                                         -- provides the clock)
    i_WRU            : in  std_logic;   -- write from GPIF
    i_WRU            : in  std_logic;   -- write from GPIF
    i_RDYU           : in  std_logic;   -- GPIF is ready
    i_RDYU           : in  std_logic;   -- GPIF is ready
    i_EOM            : in  std_logic;   -- all data for X2U transfer is in FIFO
    i_EOM            : in  std_logic;   -- all data for X2U transfer is in FIFO
    i_U2X_FULL       : in  std_logic;
    i_U2X_FULL       : in  std_logic;
    i_U2X_AM_FULL    : in  std_logic;   -- signals for IN FIFO
    i_U2X_AM_FULL    : in  std_logic;   -- signals for IN FIFO
    i_X2U_FULL_IFCLK : in  std_logic;
 
    i_X2U_AM_EMPTY   : in  std_logic;
    i_X2U_AM_EMPTY   : in  std_logic;
    i_X2U_EMPTY      : in  std_logic;   -- signals for OUT FIFO
    i_X2U_EMPTY      : in  std_logic;   -- signals for OUT FIFO
 
    o_dbus_out_mux_sel : out std_logic;
    o_bus_trans_dir  : out std_logic;
    o_bus_trans_dir  : out std_logic;
    o_U2X_WR_EN      : out std_logic;   -- signals for IN FIFO
    o_U2X_WR_EN      : out std_logic;   -- signals for IN FIFO
    o_X2U_RD_EN      : out std_logic;   -- signals for OUT FIFO
    o_X2U_RD_EN      : out std_logic;   -- signals for OUT FIFO
    o_FIFOrst        : out std_logic;
    o_FIFOrst        : out std_logic;
    o_WRX            : out std_logic;   -- To write to GPIF
    o_WRX            : out std_logic;   -- To write to GPIF
    o_RDYX           : out std_logic;   -- Core is ready
    o_RDYX           : out std_logic;   -- Core is ready
    o_ABORT          : out std_logic;  -- abort condition detected. we have to flush the data
    o_ABORT            : out std_logic;  -- abort condition detected.
 
                                         -- we have to flush the data
    o_RX             : out std_logic;
    o_RX             : out std_logic;
    o_TX             : out std_logic    --
    o_TX             : out std_logic    --
    );
    );
 
 
end gpif_com_fsm;
end gpif_com_fsm;
Line 95... Line 97...
                      inRQ, inACK, inWait, inTrans, inThrot,
                      inRQ, inACK, inWait, inTrans, inThrot,
                      inThrotBreak, inThrotEnd,
                      inThrotBreak, inThrotEnd,
                      endInTrans,
                      endInTrans,
                      -- out com states
                      -- out com states
                      outRQ, outRQdelay, outTrans, outACK, outACKwait,
                      outRQ, outRQdelay, outTrans, outACK, outACKwait,
                      outUSBwait, outUSBwaitEnd, outFIFOwait, endOutTrans);
                      outUSBwait, outFIFOwait, endOutTrans);
 
 
 
 
 
 
  signal pr_state, nx_state : t_fsmState;
  signal pr_state, nx_state : t_fsmState;
  -- XST specific synthesize attributes
  -- XST specific synthesize attributes
Line 113... Line 115...
  -- USB to Xilinx (U2X)
  -- USB to Xilinx (U2X)
  signal s_U2X_WR_EN : std_logic;
  signal s_U2X_WR_EN : std_logic;
 
 
  -- Xilinx to USB (X2U)
  -- Xilinx to USB (X2U)
  signal s_X2U_RD_EN : std_logic;
  signal s_X2U_RD_EN : std_logic;
 
  signal s_dbus_out_mux_sel : std_logic;
 
 
begin
begin
 
 
 
 
 
 
Line 125... Line 128...
  o_WRX           <= s_WRX;
  o_WRX           <= s_WRX;
  o_RDYX          <= s_RDYX;
  o_RDYX          <= s_RDYX;
  o_U2X_WR_EN     <= s_U2X_WR_EN;
  o_U2X_WR_EN     <= s_U2X_WR_EN;
  o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';
  o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';
  o_ABORT         <= s_ABORT;
  o_ABORT         <= s_ABORT;
 
  o_dbus_out_mux_sel <= s_dbus_out_mux_sel;
 
 
 
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- FSM GPIF
  -- FSM GPIF
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
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  end process action;
  end process action;
 
 
 
 
  -- comb logic
  -- comb logic
  transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
  transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
                        i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM)
                        i_X2U_EMPTY, i_EOM)
  begin  -- process transaction
  begin  -- process transaction
 
 
    -- default signal values to avoid latches:
    -- default signal values to avoid latches:
    s_FIFOrst       <= '0';
    s_FIFOrst       <= '0';
    s_bus_trans_dir <= readFromGPIF;
    s_bus_trans_dir <= readFromGPIF;
    s_U2X_WR_EN     <= '0';
    s_U2X_WR_EN     <= '0';
    s_X2U_RD_EN     <= '0';
    s_X2U_RD_EN     <= '0';
 
    s_dbus_out_mux_sel <= '0';
    nx_state        <= idle;
    nx_state        <= idle;
    s_WRX           <= '0';
    s_WRX           <= '0';
    s_RDYX          <= '0';
    s_RDYX          <= '0';
    s_ABORT         <= '0';
    s_ABORT         <= '0';
    o_RX            <= '0';
    o_RX            <= '0';
Line 172... Line 177...
        s_WRX       <= '0';
        s_WRX       <= '0';
        s_RDYX      <= '0';
        s_RDYX      <= '0';
        s_U2X_WR_EN <= '0';
        s_U2X_WR_EN <= '0';
        s_X2U_RD_EN <= '0';
        s_X2U_RD_EN <= '0';
        s_ABORT     <= '1';
        s_ABORT     <= '1';
 
        s_dbus_out_mux_sel <= '0';
        o_RX        <= '0';
        o_RX        <= '0';
        o_TX        <= '0';
        o_TX        <= '0';
        s_bus_trans_dir <= readFromGPIF;
        s_bus_trans_dir <= readFromGPIF;
 
 
        -- state decisions
        -- state decisions
Line 198... Line 204...
        if i_WRU = '1' and i_RDYU = '1' then
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
          nx_state <= rst;
        elsif i_WRU = '1' and i_RDYU = '0' then
        elsif i_WRU = '1' and i_RDYU = '0' then
          nx_state <= inRQ;
          nx_state <= inRQ;
        elsif i_WRU = '0' and
        elsif i_WRU = '0' and
          --(i_X2U_FULL_IFCLK = '1' or i_EOM = '1') and i_X2U_EMPTY = '0' then
 
          i_X2U_EMPTY = '0' then
          i_X2U_EMPTY = '0' then
          nx_state <= outRQ;
          nx_state <= outRQ;
        else
        else
          nx_state <= idle;
          nx_state <= idle;
        end if;
        end if;
Line 380... Line 385...
        -- state decisions
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
          nx_state <= rst;
        elsif i_WRU = '0' and i_RDYU = '1' then
        elsif i_WRU = '0' and i_RDYU = '1' then
          nx_state <= outTrans;
          nx_state <= outTrans;
          s_X2U_RD_EN <= '1';
 
        else
        else
          nx_state <= outACKwait;
          nx_state <= outACKwait;
        end if;
        end if;
 
 
      when outTrans =>
      when outTrans =>
Line 392... Line 396...
        s_WRX           <= '1';
        s_WRX           <= '1';
        s_RDYX          <= '0';
        s_RDYX          <= '0';
        s_X2U_RD_EN     <= '1';
        s_X2U_RD_EN     <= '1';
        o_TX            <= '1';
        o_TX            <= '1';
        s_bus_trans_dir <= writeToGPIF;
        s_bus_trans_dir <= writeToGPIF;
 
        s_dbus_out_mux_sel <= '0';
 
 
        -- state decisions
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state        <= rst;
          nx_state        <= rst;
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
Line 414... Line 419...
        s_WRX       <= '1';
        s_WRX       <= '1';
        s_RDYX      <= '0';
        s_RDYX      <= '0';
        s_X2U_RD_EN <= '0';
        s_X2U_RD_EN <= '0';
        o_TX        <= '1';
        o_TX        <= '1';
        s_bus_trans_dir <= writeToGPIF;
        s_bus_trans_dir <= writeToGPIF;
 
        s_dbus_out_mux_sel <= '1';
 
 
        -- state decisions
        -- state decisions
        if i_WRU = '1' and i_RDYU = '1' then
        if i_WRU = '1' and i_RDYU = '1' then
          nx_state <= rst;
          nx_state <= rst;
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
          nx_state <= endOutTrans;
          nx_state <= endOutTrans;
        elsif i_WRU = '0' and i_RDYU = '1' then
        elsif i_WRU = '0' and i_RDYU = '1' then
          nx_state <= outUSBwaitEnd;
          nx_state <= outTrans;
        else
        else
          nx_state <= outUSBwait;
          nx_state <= outUSBwait;
        end if;
        end if;
 
 
      when outUSBwaitEnd =>
 
        -- output signal values:
 
        s_WRX       <= '1';
 
        s_RDYX      <= '0';
 
        s_X2U_RD_EN <= '1';
 
        o_TX        <= '1';
 
        s_bus_trans_dir <= writeToGPIF;
 
 
 
        -- state decisions
 
        nx_state <= outTrans;
 
 
 
      when outFIFOwait =>
      when outFIFOwait =>
        -- output signal values:
        -- output signal values:
        s_WRX       <= '1';
        s_WRX       <= '1';
        s_RDYX      <= '1';
        s_RDYX      <= '1';
        s_X2U_RD_EN <= '0';
        s_X2U_RD_EN <= '0';
Line 452... Line 447...
          nx_state <= rst;
          nx_state <= rst;
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
        elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
          nx_state <= endOutTrans;
          nx_state <= endOutTrans;
        elsif i_X2U_EMPTY = '0' then
        elsif i_X2U_EMPTY = '0' then
          nx_state <= outTrans;
          nx_state <= outTrans;
          s_X2U_RD_EN <= '1';
 
        else
        else
          nx_state <= outFIFOwait;
          nx_state <= outFIFOwait;
        end if;
        end if;
 
 
      when endOutTrans =>
      when endOutTrans =>

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