URL https://opencores.org/ocsvn/gpib_controller/gpib_controller/trunk

Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [prototype_1/] [fpga/] [xilinx_prj/] [iseconfig/] [proto1.projectmgr] - Diff between revs 5 and 8

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Rev 5	Rev 8
Line 4...	Line 4...






`/EdgeDetector - arch`	`/EdgeDetector - arch`
`/Fifo8b - arch`	`/Fifo8b - arch`
`/Fifo8b_Test_vhd - behavior`	`/Fifo8b_Test_vhd - behavior`
`/RegsGpibFasade - arch`	`/RegsGpibFasade - arch`
`/RegsGpibFasade_communication_test - behavior`	`/RegsGpibFasade_communication_test - behavior`
`/Uart - arch`	`/Uart - arch`
`/gpibInterface - Behavioral`	`/gpibInterface - Behavioral`
`/main - Behavioral`	`/main - Behavioral`
	`/main - Behavioral/gpib0 - RegsGpibFasade - arch`
`/main - Behavioral/gpib0 - RegsGpibFasade - arch/ev - EventReg - arch`	`/main - Behavioral/gpib0 - RegsGpibFasade - arch/ev - EventReg - arch`
`/main - Behavioral/gpib0 - RegsGpibFasade - arch/gpib - gpibInterface - Behavioral`	`/main - Behavioral/gpib0 - RegsGpibFasade - arch/gpib - gpibInterface - Behavioral`
`/main - Behavioral/gpib0 - RegsGpibFasade - arch/ig - InterruptGenerator - arch`	`/main - Behavioral/gpib0 - RegsGpibFasade - arch/ig - InterruptGenerator - arch`
`/main - Behavioral/gpib0 - RegsGpibFasade - arch/rc0 - ReaderControlReg0 - arch`	`/main - Behavioral/gpib0 - RegsGpibFasade - arch/rc0 - ReaderControlReg0 - arch`
`/main - Behavioral/gpib0 - RegsGpibFasade - arch/readerFifo - Fifo8b - arch`	`/main - Behavioral/gpib0 - RegsGpibFasade - arch/readerFifo - Fifo8b - arch`
`/main - Behavioral/gpib0 - RegsGpibFasade - arch/wc0 - WriterControlReg0 - arch`	`/main - Behavioral/gpib0 - RegsGpibFasade - arch/wc0 - WriterControlReg0 - arch`
`/main - Behavioral/gpib0 - RegsGpibFasade - arch/writerFifo - Fifo8b - arch`	`/main - Behavioral/gpib0 - RegsGpibFasade - arch/writerFifo - Fifo8b - arch`


`gpib - gpibInterface - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/vhdl/src/gpib/gpibInterface.vhd)`	`main - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB_fpga/xilinx_prj/src/main.vhd)`

`0`	`0`
`0`	`0`
`000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000104000000020000000000000000000000000000000064ffffffff000000810000000000000002000001040000000100000000000000000000000100000000`	`000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000163000000020000000000000000000000000000000064ffffffff000000810000000000000002000001630000000100000000000000000000000100000000`
`true`	`true`
`gpib - gpibInterface - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/vhdl/src/gpib/gpibInterface.vhd)`	`main - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB_fpga/xilinx_prj/src/main.vhd)`



`Design Utilities/Compile HDL Simulation Libraries`	`Design Utilities/Compile HDL Simulation Libraries`
	`Implement Design`
	`Synthesize - XST`


`Add Existing Source`

`0`	`0`
`0`	`0`
`000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000`	`000000ff00000000000000010000000100000000000000000000000000000000000000000000000172000000010000000100000000000000000000000064ffffffff000000810000000000000001000001720000000100000000`
`false`	`false`
`Add Existing Source`




`0`	`0`
`0`	`0`
`000000ff00000000000000010000000000000000010000000000000000000000000000000000000250000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000001840000000100000000`	`000000ff000000000000000100000000000000000100000000000000000000000000000000000001a2000000040101000100000000000000000000000064ffffffff000000810000000000000004000000b40000000100000000000000240000000100000000000000660000000100000000000000640000000100000000`
`false`	`false`
`commandDecoder.vhd`	`main.ucf`



`work`


`0`	`0`
`0`	`0`
`000000ff00000000000000010000000000000000010000000000000000000000000000000000000128000000010001000100000000000000000000000064ffffffff000000810000000000000001000001280000000100000000`	`000000ff00000000000000010000000000000000010000000000000000000000000000000000000163000000010001000100000000000000000000000064ffffffff000000810000000000000001000001630000000100000000`
`false`	`false`
`work`	`work`



`Design Utilities`	`Design Utilities/Compile HDL Simulation Libraries`
`Implement Design`	`Implement Design`
`Synthesize - XST`	`Synthesize - XST`


`Add Existing Source`	`Generate Programming File`

`0`	`6`
`0`	`0`
`000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000`	`000000ff0000000000000001000000010000000000000000000000000000000000000000000000011b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011b0000000100000000`
`false`	`false`
`Add Existing Source`	`Generate Programming File`



`User Constraints`	`User Constraints`


`Add Existing Source`	`Add Existing Source`

`0`	`0`
`0`	`0`
`000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000`	`000000ff0000000000000001000000010000000000000000000000000000000000000000000000012a000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012a0000000100000000`
`false`	`false`
`Add Existing Source`	`Add Existing Source`

`000000ff00000000000000020000015e0000012a01000000040100000002`	`000000ff00000000000000020000015e0000012a01000000040100000002`
`Implementation`	`Implementation`

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Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [prototype_1/] [fpga/] [xilinx_prj/] [iseconfig/] [proto1.projectmgr] - Diff between revs 5 and 8