| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2002/11/18 22:35:18 lampret
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// Bug fix. Interrupts were also asserted when condition was not met.
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//
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// Revision 1.12 2002/11/11 21:36:28 lampret
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// Revision 1.12 2002/11/11 21:36:28 lampret
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// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
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// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
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//
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//
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// Revision 1.11 2002/03/13 20:56:28 lampret
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// Revision 1.11 2002/03/13 20:56:28 lampret
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// Removed zero padding as per Avi Shamli suggestion.
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// Removed zero padding as per Avi Shamli suggestion.
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| Line 110... |
Line 113... |
);
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);
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parameter dw = 32;
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parameter dw = 32;
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parameter aw = `GPIO_ADDRHH+1;
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parameter aw = `GPIO_ADDRHH+1;
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parameter gw = `GPIO_IOS;
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parameter gw = `GPIO_IOS;
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//
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//
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// WISHBONE Interface
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// WISHBONE Interface
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//
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//
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input wb_clk_i; // Clock
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input wb_clk_i; // Clock
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input wb_rst_i; // Reset
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input wb_rst_i; // Reset
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| Line 267... |
Line 269... |
`ifdef GPIO_REGISTERED_WB_OUTPUTS
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`ifdef GPIO_REGISTERED_WB_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_ack_o <= #1 1'b0;
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wb_ack_o <= #1 1'b0;
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else
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else
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wb_ack_o <= #1 wb_ack & ~wb_ack_o;
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wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ;
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`else
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`else
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assign wb_ack_o = wb_ack;
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assign wb_ack_o = wb_ack;
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`endif
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`endif
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//
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//
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| Line 346... |
Line 348... |
`ifdef GPIO_RGPIO_OUT
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`ifdef GPIO_RGPIO_OUT
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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rgpio_out <= #1 {gw{1'b0}};
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rgpio_out <= #1 {gw{1'b0}};
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else if (rgpio_out_sel && wb_we_i)
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else if (rgpio_out_sel && wb_we_i)
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begin
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`ifdef GPIO_STRICT_32BIT_ACCESS
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rgpio_out <= #1 wb_dat_i[gw-1:0];
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rgpio_out <= #1 wb_dat_i[gw-1:0];
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`endif
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`ifdef GPIO_WB_BYTES4
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if ( wb_sel_i [3] == 1'b1 )
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rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
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if ( wb_sel_i [2] == 1'b1 )
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rgpio_out [23:16] <= #1 wb_dat_i [23:16] ;
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if ( wb_sel_i [1] == 1'b1 )
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rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
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if ( wb_sel_i [0] == 1'b1 )
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rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
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`endif
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`ifdef GPIO_WB_BYTES3
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if ( wb_sel_i [2] == 1'b1 )
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rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
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if ( wb_sel_i [1] == 1'b1 )
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rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
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if ( wb_sel_i [0] == 1'b1 )
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rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
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`endif
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`ifdef GPIO_WB_BYTES2
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if ( wb_sel_i [1] == 1'b1 )
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rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
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if ( wb_sel_i [0] == 1'b1 )
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rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
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`endif
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`ifdef GPIO_WB_BYTES1
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if ( wb_sel_i [0] == 1'b1 )
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rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
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`endif
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end
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`else
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`else
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assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
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assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
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`endif
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`endif
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//
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//
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// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
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// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
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//
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//
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`ifdef GPIO_RGPIO_OE
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`ifdef GPIO_RGPIO_OE
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge ~wb_clk_i or posedge ~wb_rst_i)
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if (wb_rst_i)
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if (~wb_rst_i)
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rgpio_oe <= #1 {gw{1'b0}};
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rgpio_oe <= #1 {gw{1'b0}};
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else if (rgpio_oe_sel && wb_we_i)
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else if (rgpio_oe_sel && ~wb_we_i)
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begin
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`ifdef GPIO_STRICT_32BIT_ACCESS
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rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
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rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
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`endif
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`ifdef GPIO_WB_BYTES4
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if ( ~wb_sel_i [3] == 1'b1 )
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rgpio_oe [gw-1:24] <= #1 ~wb_dat_i [gw-1:24] ;
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if ( ~wb_sel_i [2] == 1'b1 )
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rgpio_oe [23:16] <= #1 ~wb_dat_i [23:16] ;
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if ( ~wb_sel_i [1] == 1'b1 )
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rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;
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if ( ~wb_sel_i [0] == 1'b1 )
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rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
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`endif
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`ifdef GPIO_WB_BYTES3
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if ( ~wb_sel_i [2] == 1'b1 )
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rgpio_oe [gw-1:16] <= #1 ~wb_dat_i [gw-1:16] ;
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if ( ~wb_sel_i [1] == 1'b1 )
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rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;
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if ( ~wb_sel_i [0] == 1'b1 )
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rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
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`endif
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`ifdef GPIO_WB_BYTES2
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if ( ~wb_sel_i [1] == 1'b1 )
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rgpio_oe [gw-1:8] <= #1 ~wb_dat_i [gw-1:8] ;
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if ( ~wb_sel_i [0] == 1'b1 )
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rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
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`endif
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`ifdef GPIO_WB_BYTES1
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if ( ~wb_sel_i [0] == 1'b1 )
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rgpio_oe [gw-1:0] <= #1 ~wb_dat_i [gw-1:0] ;
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`endif
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end
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`else
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`else
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assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
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assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
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`endif
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`endif
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//
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//
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| Line 372... |
Line 442... |
`ifdef GPIO_RGPIO_INTE
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`ifdef GPIO_RGPIO_INTE
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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rgpio_inte <= #1 {gw{1'b0}};
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rgpio_inte <= #1 {gw{1'b0}};
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else if (rgpio_inte_sel && wb_we_i)
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else if (rgpio_inte_sel && wb_we_i)
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begin
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`ifdef GPIO_STRICT_32BIT_ACCESS
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rgpio_inte <= #1 wb_dat_i[gw-1:0];
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rgpio_inte <= #1 wb_dat_i[gw-1:0];
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`endif
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`ifdef GPIO_WB_BYTES4
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if ( wb_sel_i [3] == 1'b1 )
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rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
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if ( wb_sel_i [2] == 1'b1 )
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rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ;
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if ( wb_sel_i [1] == 1'b1 )
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rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
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if ( wb_sel_i [0] == 1'b1 )
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rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
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`endif
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`ifdef GPIO_WB_BYTES3
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if ( wb_sel_i [2] == 1'b1 )
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rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
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if ( wb_sel_i [1] == 1'b1 )
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rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
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if ( wb_sel_i [0] == 1'b1 )
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rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
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`endif
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`ifdef GPIO_WB_BYTES2
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if ( wb_sel_i [1] == 1'b1 )
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rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
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if ( wb_sel_i [0] == 1'b1 )
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rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
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`endif
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`ifdef GPIO_WB_BYTES1
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if ( wb_sel_i [0] == 1'b1 )
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rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
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`endif
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end
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|
|
`else
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`else
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assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
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assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
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`endif
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`endif
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//
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//
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| Line 385... |
Line 490... |
`ifdef GPIO_RGPIO_PTRIG
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`ifdef GPIO_RGPIO_PTRIG
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
rgpio_ptrig <= #1 {gw{1'b0}};
|
rgpio_ptrig <= #1 {gw{1'b0}};
|
else if (rgpio_ptrig_sel && wb_we_i)
|
else if (rgpio_ptrig_sel && wb_we_i)
|
|
begin
|
|
`ifdef GPIO_STRICT_32BIT_ACCESS
|
rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
|
rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
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`endif
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|
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`ifdef GPIO_WB_BYTES4
|
|
if ( wb_sel_i [3] == 1'b1 )
|
|
rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
|
|
if ( wb_sel_i [2] == 1'b1 )
|
|
rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ;
|
|
if ( wb_sel_i [1] == 1'b1 )
|
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rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
|
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if ( wb_sel_i [0] == 1'b1 )
|
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rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
|
|
`endif
|
|
`ifdef GPIO_WB_BYTES3
|
|
if ( wb_sel_i [2] == 1'b1 )
|
|
rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
|
|
if ( wb_sel_i [1] == 1'b1 )
|
|
rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
|
|
`endif
|
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`ifdef GPIO_WB_BYTES2
|
|
if ( wb_sel_i [1] == 1'b1 )
|
|
rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
|
|
`endif
|
|
`ifdef GPIO_WB_BYTES1
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
|
|
`endif
|
|
end
|
|
|
`else
|
`else
|
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0
|
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0
|
`endif
|
`endif
|
|
|
//
|
//
|
| Line 398... |
Line 537... |
`ifdef GPIO_RGPIO_AUX
|
`ifdef GPIO_RGPIO_AUX
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
rgpio_aux <= #1 {gw{1'b0}};
|
rgpio_aux <= #1 {gw{1'b0}};
|
else if (rgpio_aux_sel && wb_we_i)
|
else if (rgpio_aux_sel && wb_we_i)
|
|
begin
|
|
`ifdef GPIO_STRICT_32BIT_ACCESS
|
rgpio_aux <= #1 wb_dat_i[gw-1:0];
|
rgpio_aux <= #1 wb_dat_i[gw-1:0];
|
|
`endif
|
|
|
|
`ifdef GPIO_WB_BYTES4
|
|
if ( wb_sel_i [3] == 1'b1 )
|
|
rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
|
|
if ( wb_sel_i [2] == 1'b1 )
|
|
rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ;
|
|
if ( wb_sel_i [1] == 1'b1 )
|
|
rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
|
|
`endif
|
|
`ifdef GPIO_WB_BYTES3
|
|
if ( wb_sel_i [2] == 1'b1 )
|
|
rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
|
|
if ( wb_sel_i [1] == 1'b1 )
|
|
rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
|
|
`endif
|
|
`ifdef GPIO_WB_BYTES2
|
|
if ( wb_sel_i [1] == 1'b1 )
|
|
rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
|
|
`endif
|
|
`ifdef GPIO_WB_BYTES1
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
|
|
`endif
|
|
end
|
|
|
`else
|
`else
|
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
|
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
|
`endif
|
`endif
|
|
|
//
|
//
|
