URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

[/] [gpio/] [tags/] [rel_11/] [bench/] [verilog/] [wb_master.v] - Diff between revs 8 and 37

Rev 8	Rev 37
Line 1...	Line 1...
`include "timescale.v"	`include "timescale.v"
	`include "gpio_defines.v"

`// -- Mode: Verilog --`	`// -- Mode: Verilog --`
`// Filename : wb_master.v`	`// Filename : wb_master.v`
`// Description : Wishbone Master Behavorial`	`// Description : Wishbone Master Behavorial`
`// Author : Winefred Washington`	`// Author : Winefred Washington`
Line 23...	Line 24...
`//`	`//`

`module wb_master(CLK_I, RST_I, TAG_I, TAG_O,`	`module wb_master(CLK_I, RST_I, TAG_I, TAG_O,`
`ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O);`	`ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O);`

	parameter aw = `GPIO_ADDRHH+1 ;
`input CLK_I;`	`input CLK_I;`
`input RST_I;`	`input RST_I;`
`input [3:0] TAG_I;`	`input [3:0] TAG_I;`
`output [3:0] TAG_O;`	`output [3:0] TAG_O;`
`input ACK_I;`	`input ACK_I;`
`output [31:0] ADR_O;`	`output [aw-1:0] ADR_O;`
`output CYC_O;`	`output CYC_O;`
`input [31:0] DAT_I;`	`input [31:0] DAT_I;`
`output [31:0] DAT_O;`	`output [31:0] DAT_O;`
`input ERR_I;`	`input ERR_I;`
`input RTY_I;`	`input RTY_I;`
`output [3:0] SEL_O;`	`output [3:0] SEL_O;`
`output STB_O;`	`output STB_O;`
`output WE_O;`	`output WE_O;`

`reg [31:0] ADR_O;`	`reg [aw-1:0] ADR_O;`
`reg [3:0] SEL_O;`	`reg [3:0] SEL_O;`
`reg CYC_O;`	`reg CYC_O;`
`reg STB_O;`	`reg STB_O;`
`reg WE_O;`	`reg WE_O;`
`reg [31:0] DAT_O;`	`reg [31:0] DAT_O;`