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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2003/12/17 13:00:52 gorand
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// added ECLK and NEC registers, all tests passed.
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//
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// Revision 1.7 2003/12/01 17:10:44 simons
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// Revision 1.7 2003/12/01 17:10:44 simons
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// ifndef directive is not supported by all tools.
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// ifndef directive is not supported by all tools.
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//
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//
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// Revision 1.6 2003/11/06 13:59:07 gorand
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// Revision 1.6 2003/11/06 13:59:07 gorand
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// added support for 8-bit access to registers.
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// added support for 8-bit access to registers.
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| Line 136... |
Line 139... |
// this macro. By default it is defined.
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// this macro. By default it is defined.
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//
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//
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`define GPIO_REGISTERED_IO_OUTPUTS
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`define GPIO_REGISTERED_IO_OUTPUTS
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//
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//
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// Implement aux feature. If this define is not defined also aux_i port and
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// RGPIO_AUX register will be removed
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//
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// Defined by default.
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//
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`define GPIO_AUX_IMPLEMENT
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//
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// If this is not defined clk_pad_i will be removed. Input lines will be lached on
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// positive edge of system clock
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// if disabled defines GPIO_NO_NEGEDGE_FLOPS, GPIO_NO_CLKPAD_LOGIC will have no effect.
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//
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// Defined by default.
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//
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`define GPIO_CLKPAD
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//
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// Define to avoid using negative edge clock flip-flops for external clock
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// Define to avoid using negative edge clock flip-flops for external clock
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// (caused by NEC register. Instead an inverted external clock with
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// (caused by NEC register. Instead an inverted external clock with
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// positive edge clock flip-flops will be used.
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// positive edge clock flip-flops will be used.
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// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined
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//
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//
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// By default it is not defined.
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// By default it is not defined.
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//
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//
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//`define GPIO_NO_NEGEDGE_FLOPS
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//`define GPIO_NO_NEGEDGE_FLOPS
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//
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//
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// If GPIO_NO_NEGEDGE_FLOPS is defined, a mux needs to be placed on external clock
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// If GPIO_NO_NEGEDGE_FLOPS is defined, a mux needs to be placed on external clock
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// clk_pad_i to implement RGPIO_CTRL[NEC] functionality. If no mux is allowed on
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// clk_pad_i to implement RGPIO_CTRL[NEC] functionality. If no mux is allowed on
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// clock signal, enable the following define.
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// clock signal, enable the following define.
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// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined
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//
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//
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// By default it is not defined.
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// By default it is not defined.
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//
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//
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//`define GPIO_NO_CLKPAD_LOGIC
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//`define GPIO_NO_CLKPAD_LOGIC
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//
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// synchronization defines
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//
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// Two synchronization flops to input lineis added.
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// system clock synchronization.
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//
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`define GPIO_SYNC_IN_WB
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//
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// Add synchronization flops to external clock input line. Gpio will have just one clock domain,
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// everithing will be synchronized to wishbone clock. External clock muas be at least 2-3x slower
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// as systam clock.
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//
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`define GPIO_SYNC_CLK_WB
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//
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// Add synchronization to input pads. synchronization to external clock.
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// Don't hawe any effect if GPIO_SYNC_CLK_WB is defined.
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//
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//`define GPIO_SYNC_IN_CLK
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//
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// Add synchronization flops between system clock and external clock.
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// Only possible if external clock is enabled and clock synchroization is disabled.
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//
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//`define GPIO_SYNC_IN_CLK_WB
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//
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//
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// Undefine if you don't need to read GPIO registers except for RGPIO_IN register.
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// Undefine if you don't need to read GPIO registers except for RGPIO_IN register.
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// When it is undefined all reads of GPIO registers return RGPIO_IN register. This
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// When it is undefined all reads of GPIO registers return RGPIO_IN register. This
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// is usually useful if you want really small area (for example when implemented in
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// is usually useful if you want really small area (for example when implemented in
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// FPGA).
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// FPGA).
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| Line 196... |
Line 248... |
// if the number of I/O lines is in range 9-16, GPIO_WB_BYTES2 is defined,
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// if the number of I/O lines is in range 9-16, GPIO_WB_BYTES2 is defined,
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// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined,
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// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined,
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// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined,
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// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined,
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`define GPIO_WB_BYTES4
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`define GPIO_WB_BYTES4
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//`define GPIO_WB_BYTES3
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//`define GPIO_WB_BYTES2
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//`define GPIO_WB_BYTES1
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`endif
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`endif
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//
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//
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// WISHBONE address bits used for full decoding of GPIO registers.
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// WISHBONE address bits used for full decoding of GPIO registers.
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//
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//
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| Line 229... |
Line 285... |
`define GPIO_RGPIO_IN 4'h0 // Address 0x00
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`define GPIO_RGPIO_IN 4'h0 // Address 0x00
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`define GPIO_RGPIO_OUT 4'h1 // Address 0x04
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`define GPIO_RGPIO_OUT 4'h1 // Address 0x04
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`define GPIO_RGPIO_OE 4'h2 // Address 0x08
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`define GPIO_RGPIO_OE 4'h2 // Address 0x08
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`define GPIO_RGPIO_INTE 4'h3 // Address 0x0c
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`define GPIO_RGPIO_INTE 4'h3 // Address 0x0c
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`define GPIO_RGPIO_PTRIG 4'h4 // Address 0x10
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`define GPIO_RGPIO_PTRIG 4'h4 // Address 0x10
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`ifdef GPIO_AUX_IMPLEMENT
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`define GPIO_RGPIO_AUX 4'h5 // Address 0x14
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`define GPIO_RGPIO_AUX 4'h5 // Address 0x14
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`endif // GPIO_AUX_IMPLEMENT
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`define GPIO_RGPIO_CTRL 4'h6 // Address 0x18
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`define GPIO_RGPIO_CTRL 4'h6 // Address 0x18
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`define GPIO_RGPIO_INTS 4'h7 // Address 0x1c
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`define GPIO_RGPIO_INTS 4'h7 // Address 0x1c
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`ifdef GPIO_CLKPAD
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`define GPIO_RGPIO_ECLK 4'h8 // Address 0x20
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`define GPIO_RGPIO_ECLK 4'h8 // Address 0x20
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`define GPIO_RGPIO_NEC 4'h9 // Address 0x24
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`define GPIO_RGPIO_NEC 4'h9 // Address 0x24
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`endif // GPIO_CLKPAD
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//
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//
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// Default values for unimplemented GPIO registers
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// Default values for unimplemented GPIO registers
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//
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//
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`define GPIO_DEF_RGPIO_IN `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_IN `GPIO_IOS'h0
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| Line 258... |
Line 321... |
// bit 0 to bit 1 in the following order: INTE, INT
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// bit 0 to bit 1 in the following order: INTE, INT
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//
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//
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`define GPIO_RGPIO_CTRL_INTE 0
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`define GPIO_RGPIO_CTRL_INTE 0
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`define GPIO_RGPIO_CTRL_INTS 1
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`define GPIO_RGPIO_CTRL_INTS 1
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`ifdef GPIO_LINES32
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`define GPIO_LINES31
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`endif
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`ifdef GPIO_LINES31
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`define GPIO_LINES30
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`endif
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`ifdef GPIO_LINES30
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`define GPIO_LINES29
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`endif
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`ifdef GPIO_LINES29
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`define GPIO_LINES28
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`endif
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`ifdef GPIO_LINES28
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`define GPIO_LINES27
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`endif
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`ifdef GPIO_LINES27
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`define GPIO_LINES26
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`endif
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`ifdef GPIO_LINES26
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`define GPIO_LINES25
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`endif
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`ifdef GPIO_LINES25
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`define GPIO_LINES24
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`endif
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`ifdef GPIO_LINES24
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`define GPIO_LINES23
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`endif
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`ifdef GPIO_LINES23
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`define GPIO_LINES22
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`endif
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`ifdef GPIO_LINES22
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`define GPIO_LINES21
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`endif
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`ifdef GPIO_LINES21
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`define GPIO_LINES20
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`endif
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`ifdef GPIO_LINES20
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`define GPIO_LINES19
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`endif
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`ifdef GPIO_LINES19
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`define GPIO_LINES18
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`endif
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`ifdef GPIO_LINES18
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`define GPIO_LINES17
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`endif
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`ifdef GPIO_LINES17
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`define GPIO_LINES16
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`endif
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`ifdef GPIO_LINES16
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`define GPIO_LINES15
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`endif
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`ifdef GPIO_LINES15
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`define GPIO_LINES14
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`endif
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`ifdef GPIO_LINES14
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`define GPIO_LINES13
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`endif
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`ifdef GPIO_LINES13
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`define GPIO_LINES12
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`endif
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`ifdef GPIO_LINES12
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`define GPIO_LINES11
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`endif
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`ifdef GPIO_LINES11
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`define GPIO_LINES10
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`endif
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`ifdef GPIO_LINES10
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`define GPIO_LINES9
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`endif
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`ifdef GPIO_LINES9
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`define GPIO_LINES8
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`endif
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`ifdef GPIO_LINES8
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`define GPIO_LINES7
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`endif
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`ifdef GPIO_LINES7
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`define GPIO_LINES6
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`endif
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`ifdef GPIO_LINES6
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`define GPIO_LINES5
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`endif
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`ifdef GPIO_LINES5
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`define GPIO_LINES4
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`endif
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`ifdef GPIO_LINES4
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`define GPIO_LINES3
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`endif
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`ifdef GPIO_LINES3
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`define GPIO_LINES2
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`endif
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`ifdef GPIO_LINES2
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`define GPIO_LINES1
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`endif
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No newline at end of file
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No newline at end of file
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