Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.14 2003/11/06 13:59:07 gorand
|
|
// added support for 8-bit access to registers.
|
|
//
|
// Revision 1.13 2002/11/18 22:35:18 lampret
|
// Revision 1.13 2002/11/18 22:35:18 lampret
|
// Bug fix. Interrupts were also asserted when condition was not met.
|
// Bug fix. Interrupts were also asserted when condition was not met.
|
//
|
//
|
// Revision 1.12 2002/11/11 21:36:28 lampret
|
// Revision 1.12 2002/11/11 21:36:28 lampret
|
// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
|
// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
|
Line 391... |
Line 394... |
|
|
//
|
//
|
// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
|
// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
|
//
|
//
|
`ifdef GPIO_RGPIO_OE
|
`ifdef GPIO_RGPIO_OE
|
always @(posedge ~wb_clk_i or posedge ~wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (~wb_rst_i)
|
if (wb_rst_i)
|
rgpio_oe <= #1 {gw{1'b0}};
|
rgpio_oe <= #1 {gw{1'b0}};
|
else if (rgpio_oe_sel && ~wb_we_i)
|
else if (rgpio_oe_sel && wb_we_i)
|
begin
|
begin
|
`ifdef GPIO_STRICT_32BIT_ACCESS
|
`ifdef GPIO_STRICT_32BIT_ACCESS
|
rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
|
rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
|
`endif
|
`endif
|
|
|
`ifdef GPIO_WB_BYTES4
|
`ifdef GPIO_WB_BYTES4
|
if ( ~wb_sel_i [3] == 1'b1 )
|
if ( wb_sel_i [3] == 1'b1 )
|
rgpio_oe [gw-1:24] <= #1 ~wb_dat_i [gw-1:24] ;
|
rgpio_oe [gw-1:24] <= #1 ~wb_dat_i [gw-1:24] ;
|
if ( ~wb_sel_i [2] == 1'b1 )
|
if ( wb_sel_i [2] == 1'b1 )
|
rgpio_oe [23:16] <= #1 ~wb_dat_i [23:16] ;
|
rgpio_oe [23:16] <= #1 ~wb_dat_i [23:16] ;
|
if ( ~wb_sel_i [1] == 1'b1 )
|
if ( wb_sel_i [1] == 1'b1 )
|
rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;
|
rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;
|
if ( ~wb_sel_i [0] == 1'b1 )
|
if ( wb_sel_i [0] == 1'b1 )
|
rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
|
rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
|
`endif
|
`endif
|
`ifdef GPIO_WB_BYTES3
|
`ifdef GPIO_WB_BYTES3
|
if ( ~wb_sel_i [2] == 1'b1 )
|
if ( wb_sel_i [2] == 1'b1 )
|
rgpio_oe [gw-1:16] <= #1 ~wb_dat_i [gw-1:16] ;
|
rgpio_oe [gw-1:16] <= #1 ~wb_dat_i [gw-1:16] ;
|
if ( ~wb_sel_i [1] == 1'b1 )
|
if ( wb_sel_i [1] == 1'b1 )
|
rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;
|
rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;
|
if ( ~wb_sel_i [0] == 1'b1 )
|
if ( wb_sel_i [0] == 1'b1 )
|
rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
|
rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
|
`endif
|
`endif
|
`ifdef GPIO_WB_BYTES2
|
`ifdef GPIO_WB_BYTES2
|
if ( ~wb_sel_i [1] == 1'b1 )
|
if ( wb_sel_i [1] == 1'b1 )
|
rgpio_oe [gw-1:8] <= #1 ~wb_dat_i [gw-1:8] ;
|
rgpio_oe [gw-1:8] <= #1 ~wb_dat_i [gw-1:8] ;
|
if ( ~wb_sel_i [0] == 1'b1 )
|
if ( wb_sel_i [0] == 1'b1 )
|
rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
|
rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;
|
`endif
|
`endif
|
`ifdef GPIO_WB_BYTES1
|
`ifdef GPIO_WB_BYTES1
|
if ( ~wb_sel_i [0] == 1'b1 )
|
if ( wb_sel_i [0] == 1'b1 )
|
rgpio_oe [gw-1:0] <= #1 ~wb_dat_i [gw-1:0] ;
|
rgpio_oe [gw-1:0] <= #1 ~wb_dat_i [gw-1:0] ;
|
`endif
|
`endif
|
end
|
end
|
|
|
`else
|
`else
|