| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.17 2004/05/05 08:21:00 andreje
|
|
// Bugfixes when GPIO_RGPIO_ECLK/GPIO_RGPIO_NEC disabled, gpio oe name change and set to active-high according to spec
|
|
//
|
// Revision 1.16 2003/12/17 13:00:52 gorand
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// Revision 1.16 2003/12/17 13:00:52 gorand
|
// added ECLK and NEC registers, all tests passed.
|
// added ECLK and NEC registers, all tests passed.
|
//
|
//
|
// Revision 1.15 2003/11/10 23:21:22 gorand
|
// Revision 1.15 2003/11/10 23:21:22 gorand
|
// bug fixed. all tests passed.
|
// bug fixed. all tests passed.
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| Line 112... |
Line 115... |
module gpio_top(
|
module gpio_top(
|
// WISHBONE Interface
|
// WISHBONE Interface
|
wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
|
wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
|
wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
|
wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
|
|
|
|
`ifdef GPIO_AUX_IMPLEMENT
|
// Auxiliary inputs interface
|
// Auxiliary inputs interface
|
aux_i,
|
aux_i,
|
|
`endif // GPIO_AUX_IMPLEMENT
|
|
|
// External GPIO Interface
|
// External GPIO Interface
|
ext_pad_i, clk_pad_i, ext_pad_o, ext_padoe_o
|
ext_pad_i, ext_pad_o, ext_padoe_o
|
|
`ifdef GPIO_CLKPAD
|
|
, clk_pad_i
|
|
`endif
|
);
|
);
|
|
|
parameter dw = 32;
|
parameter dw = 32;
|
parameter aw = `GPIO_ADDRHH+1;
|
parameter aw = `GPIO_ADDRHH+1;
|
parameter gw = `GPIO_IOS;
|
parameter gw = `GPIO_IOS;
|
| Line 138... |
Line 146... |
output [dw-1:0] wb_dat_o; // output data bus
|
output [dw-1:0] wb_dat_o; // output data bus
|
output wb_ack_o; // normal termination
|
output wb_ack_o; // normal termination
|
output wb_err_o; // termination w/ error
|
output wb_err_o; // termination w/ error
|
output wb_inta_o; // Interrupt request output
|
output wb_inta_o; // Interrupt request output
|
|
|
|
`ifdef GPIO_AUX_IMPLEMENT
|
// Auxiliary Inputs Interface
|
// Auxiliary Inputs Interface
|
input [gw-1:0] aux_i; // Auxiliary inputs
|
input [gw-1:0] aux_i; // Auxiliary inputs
|
|
`endif // GPIO_AUX_IMPLEMENT
|
|
|
//
|
//
|
// External GPIO Interface
|
// External GPIO Interface
|
//
|
//
|
input [gw-1:0] ext_pad_i; // GPIO Inputs
|
input [gw-1:0] ext_pad_i; // GPIO Inputs
|
|
`ifdef GPIO_CLKPAD
|
input clk_pad_i; // GPIO Eclk
|
input clk_pad_i; // GPIO Eclk
|
|
`endif // GPIO_CLKPAD
|
output [gw-1:0] ext_pad_o; // GPIO Outputs
|
output [gw-1:0] ext_pad_o; // GPIO Outputs
|
output [gw-1:0] ext_padoe_o; // GPIO output drivers enables
|
output [gw-1:0] ext_padoe_o; // GPIO output drivers enables
|
|
|
`ifdef GPIO_IMPLEMENTED
|
`ifdef GPIO_IMPLEMENTED
|
|
|
| Line 241... |
Line 253... |
reg [gw-1:0] rgpio_nec; // RGPIO_NEC register
|
reg [gw-1:0] rgpio_nec; // RGPIO_NEC register
|
`else
|
`else
|
wire [gw-1:0] rgpio_nec; // No register
|
wire [gw-1:0] rgpio_nec; // No register
|
`endif
|
`endif
|
|
|
|
|
|
//
|
|
// Synchronization flops for input signals
|
|
//
|
|
`ifdef GPIO_SYNC_IN_WB
|
|
reg [gw-1:0] sync ,
|
|
ext_pad_s ;
|
|
`else
|
|
wire [gw-1:0] ext_pad_s ;
|
|
`endif
|
|
|
|
|
|
|
//
|
//
|
// Internal wires & regs
|
// Internal wires & regs
|
//
|
//
|
wire rgpio_out_sel; // RGPIO_OUT select
|
wire rgpio_out_sel; // RGPIO_OUT select
|
wire rgpio_oe_sel; // RGPIO_OE select
|
wire rgpio_oe_sel; // RGPIO_OE select
|
| Line 269... |
Line 294... |
`endif
|
`endif
|
wire [gw-1:0] out_pad; // GPIO Outputs
|
wire [gw-1:0] out_pad; // GPIO Outputs
|
`ifdef GPIO_REGISTERED_IO_OUTPUTS
|
`ifdef GPIO_REGISTERED_IO_OUTPUTS
|
reg [gw-1:0] ext_pad_o; // GPIO Outputs
|
reg [gw-1:0] ext_pad_o; // GPIO Outputs
|
`endif
|
`endif
|
|
`ifdef GPIO_CLKPAD
|
wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock
|
wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock
|
wire [gw-1:0] pext_clk; // External clock for posedge flops
|
wire [gw-1:0] pext_clk; // External clock for posedge flops
|
reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs
|
reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
|
`ifdef GPIO_NO_CLKPAD_LOGIC
|
|
`else
|
|
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
|
|
`endif // GPIO_NO_CLKPAD_LOGIC
|
`else
|
`else
|
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
|
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
|
`endif
|
`endif
|
|
`endif // GPIO_CLKPAD
|
|
|
|
|
//
|
//
|
// All WISHBONE transfer terminations are successful except when:
|
// All WISHBONE transfer terminations are successful except when:
|
// a) full address decoding is enabled and address doesn't match
|
// a) full address decoding is enabled and address doesn't match
|
| Line 725... |
Line 756... |
|
|
`else
|
`else
|
assign rgpio_nec = `GPIO_DEF_RGPIO_NEC; // RGPIO_NEC = 0x0
|
assign rgpio_nec = `GPIO_DEF_RGPIO_NEC; // RGPIO_NEC = 0x0
|
`endif
|
`endif
|
|
|
|
//
|
|
// synchronize inputs to systam clock
|
|
//
|
|
`ifdef GPIO_SYNC_IN_WB
|
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
|
if (wb_rst_i) begin
|
|
sync <= #1 {gw{1'b0}} ;
|
|
ext_pad_s <= #1 {gw{1'b0}} ;
|
|
end else begin
|
|
sync <= #1 ext_pad_i ;
|
|
ext_pad_s <= #1 sync ;
|
|
end
|
|
`else
|
|
assign ext_pad_s = ext_pad_i;
|
|
`endif // GPIO_SYNC_IN_WB
|
|
|
//
|
//
|
// Latch into RGPIO_IN
|
// Latch into RGPIO_IN
|
//
|
//
|
`ifdef GPIO_RGPIO_IN
|
`ifdef GPIO_RGPIO_IN
|
| Line 739... |
Line 785... |
rgpio_in <= #1 in_muxed;
|
rgpio_in <= #1 in_muxed;
|
`else
|
`else
|
assign rgpio_in = in_muxed;
|
assign rgpio_in = in_muxed;
|
`endif
|
`endif
|
|
|
//
|
`ifdef GPIO_CLKPAD
|
// Mux inputs directly from input pads with inputs sampled by external clock
|
|
//
|
|
//assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
|
|
|
|
|
|
`ifdef GPIO_LINES32
|
|
assign in_muxed [31] = rgpio_eclk [31] ? extc_in[31] : ext_pad_i[31] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES31
|
|
assign in_muxed [30] = rgpio_eclk [30] ? extc_in[30] : ext_pad_i[30] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES30
|
|
assign in_muxed [29] = rgpio_eclk [29] ? extc_in[29] : ext_pad_i[29] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES29
|
|
assign in_muxed [28] = rgpio_eclk [28] ? extc_in[28] : ext_pad_i[28] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES28
|
|
assign in_muxed [27] = rgpio_eclk [27] ? extc_in[27] : ext_pad_i[27] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES27
|
|
assign in_muxed [26] = rgpio_eclk [26] ? extc_in[26] : ext_pad_i[26] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES26
|
|
assign in_muxed [25] = rgpio_eclk [25] ? extc_in[25] : ext_pad_i[25] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES25
|
|
assign in_muxed [24] = rgpio_eclk [24] ? extc_in[24] : ext_pad_i[24] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES24
|
|
assign in_muxed [23] = rgpio_eclk [23] ? extc_in[23] : ext_pad_i[23] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES23
|
|
assign in_muxed [22] = rgpio_eclk [22] ? extc_in[22] : ext_pad_i[22] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES22
|
|
assign in_muxed [21] = rgpio_eclk [21] ? extc_in[21] : ext_pad_i[21] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES21
|
|
assign in_muxed [20] = rgpio_eclk [20] ? extc_in[20] : ext_pad_i[20] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES20
|
`ifdef GPIO_SYNC_CLK_WB
|
assign in_muxed [19] = rgpio_eclk [19] ? extc_in[19] : ext_pad_i[19] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES19
|
|
assign in_muxed [18] = rgpio_eclk [18] ? extc_in[18] : ext_pad_i[18] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES18
|
|
assign in_muxed [17] = rgpio_eclk [17] ? extc_in[17] : ext_pad_i[17] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES17
|
|
assign in_muxed [16] = rgpio_eclk [16] ? extc_in[16] : ext_pad_i[16] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES16
|
|
assign in_muxed [15] = rgpio_eclk [15] ? extc_in[15] : ext_pad_i[15] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES15
|
|
assign in_muxed [14] = rgpio_eclk [14] ? extc_in[14] : ext_pad_i[14] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES14
|
|
assign in_muxed [13] = rgpio_eclk [13] ? extc_in[13] : ext_pad_i[13] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES13
|
|
assign in_muxed [12] = rgpio_eclk [12] ? extc_in[12] : ext_pad_i[12] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES12
|
|
assign in_muxed [11] = rgpio_eclk [11] ? extc_in[11] : ext_pad_i[11] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES11
|
|
assign in_muxed [10] = rgpio_eclk [10] ? extc_in[10] : ext_pad_i[10] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES10
|
|
assign in_muxed [9] = rgpio_eclk [9] ? extc_in[9] : ext_pad_i[9] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES9
|
|
assign in_muxed [8] = rgpio_eclk [8] ? extc_in[8] : ext_pad_i[8] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES8
|
|
assign in_muxed [7] = rgpio_eclk [7] ? extc_in[7] : ext_pad_i[7] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES7
|
|
assign in_muxed [6] = rgpio_eclk [6] ? extc_in[6] : ext_pad_i[6] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES6
|
|
assign in_muxed [5] = rgpio_eclk [5] ? extc_in[5] : ext_pad_i[5] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES5
|
|
assign in_muxed [4] = rgpio_eclk [4] ? extc_in[4] : ext_pad_i[4] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES4
|
|
assign in_muxed [3] = rgpio_eclk [3] ? extc_in[3] : ext_pad_i[3] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES3
|
|
assign in_muxed [2] = rgpio_eclk [2] ? extc_in[2] : ext_pad_i[2] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES2
|
|
assign in_muxed [1] = rgpio_eclk [1] ? extc_in[1] : ext_pad_i[1] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES1
|
|
assign in_muxed [0] = rgpio_eclk [0] ? extc_in[0] : ext_pad_i[0] ;
|
|
`endif
|
|
|
|
|
|
//
|
|
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
|
|
// If negedge flops are allowed, pext_clk only clocks posedge flops.
|
|
//
|
//
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
// external clock enabled
|
`ifdef GPIO_NO_CLKPAD_LOGIC
|
// synchronized to system clock
|
assign pext_clk = {gw{clk_pad_i}};
|
// (one clock domain)
|
`else
|
//
|
|
|
//assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
|
reg sync_clk,
|
|
clk_s ,
|
|
clk_r ;
|
`ifdef GPIO_LINES32
|
wire pedge ,
|
assign pext_clk [31] = rgpio_nec [31] ? ~clk_pad_i : clk_pad_i ;
|
nedge ;
|
`endif
|
wire [gw-1:0] pedge_vec ,
|
|
nedge_vec ;
|
`ifdef GPIO_LINES31
|
wire [gw-1:0] in_lach ;
|
assign pext_clk [30] = rgpio_nec [30] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
assign pedge = clk_s & !clk_r ;
|
|
assign nedge = !clk_s & clk_r ;
|
`ifdef GPIO_LINES30
|
assign pedge_vec = {gw{pedge}} ;
|
assign pext_clk [29] = rgpio_nec [29] ? ~clk_pad_i : clk_pad_i ;
|
assign nedge_vec = {gw{nedge}} ;
|
`endif
|
|
|
|
`ifdef GPIO_LINES29
|
|
assign pext_clk [28] = rgpio_nec [28] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES28
|
|
assign pext_clk [27] = rgpio_nec [27] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES27
|
|
assign pext_clk [26] = rgpio_nec [26] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES26
|
|
assign pext_clk [25] = rgpio_nec [25] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES25
|
|
assign pext_clk [24] = rgpio_nec [24] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES24
|
|
assign pext_clk [23] = rgpio_nec [23] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES23
|
|
assign pext_clk [22] = rgpio_nec [22] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES22
|
|
assign pext_clk [21] = rgpio_nec [21] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES21
|
|
assign pext_clk [20] = rgpio_nec [20] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES20
|
|
assign pext_clk [19] = rgpio_nec [19] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES19
|
|
assign pext_clk [18] = rgpio_nec [18] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES18
|
|
assign pext_clk [17] = rgpio_nec [17] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES17
|
|
assign pext_clk [16] = rgpio_nec [16] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES16
|
|
assign pext_clk [15] = rgpio_nec [15] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES15
|
|
assign pext_clk [14] = rgpio_nec [14] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES14
|
|
assign pext_clk [13] = rgpio_nec [13] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES13
|
|
assign pext_clk [12] = rgpio_nec [12] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES12
|
|
assign pext_clk [11] = rgpio_nec [11] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES11
|
|
assign pext_clk [10] = rgpio_nec [10] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES10
|
|
assign pext_clk [9] = rgpio_nec [9] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES9
|
|
assign pext_clk [8] = rgpio_nec [8] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES8
|
|
assign pext_clk [7] = rgpio_nec [7] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES7
|
|
assign pext_clk [6] = rgpio_nec [6] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES6
|
assign in_lach = (~rgpio_nec & pedge_vec) | (rgpio_nec & nedge_vec) ;
|
assign pext_clk [5] = rgpio_nec [5] ? ~clk_pad_i : clk_pad_i ;
|
assign extc_in = (in_lach & ext_pad_s) | (~in_lach & pextc_sampled) ;
|
`endif
|
|
|
|
`ifdef GPIO_LINES5
|
|
assign pext_clk [4] = rgpio_nec [4] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES4
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
assign pext_clk [3] = rgpio_nec [3] ? ~clk_pad_i : clk_pad_i ;
|
if (wb_rst_i) begin
|
`endif
|
sync_clk <= #1 1'b0 ;
|
|
clk_s <= #1 1'b0 ;
|
`ifdef GPIO_LINES3
|
clk_r <= #1 1'b0 ;
|
assign pext_clk [2] = rgpio_nec [2] ? ~clk_pad_i : clk_pad_i ;
|
end else begin
|
`endif
|
sync_clk <= #1 clk_pad_i ;
|
|
clk_s <= #1 sync_clk ;
|
|
clk_r <= #1 clk_s ;
|
|
end
|
|
|
`ifdef GPIO_LINES2
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
assign pext_clk [1] = rgpio_nec [1] ? ~clk_pad_i : clk_pad_i ;
|
if (wb_rst_i) begin
|
`endif
|
pextc_sampled <= #1 {gw{1'b0}};
|
|
end else begin
|
|
pextc_sampled <= #1 extc_in ;
|
|
end
|
|
|
`ifdef GPIO_LINES1
|
assign in_muxed = (rgpio_eclk & pextc_sampled) | (~rgpio_eclk & ext_pad_s) ;
|
assign pext_clk [0] = rgpio_nec [0] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`endif
|
|
`else
|
`else
|
assign pext_clk = {gw{clk_pad_i}};
|
|
`endif
|
|
|
|
|
|
//
|
//
|
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
|
// external clock enabled
|
|
// not synchronized to system clock
|
|
// (two clock domains)
|
//
|
//
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
|
assign extc_in = pextc_sampled;
|
|
`else
|
|
//assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
|
|
|
|
|
|
`ifdef GPIO_LINES32
|
|
assign extc_in [31] = rgpio_nec [31] ? nextc_sampled[31] : pextc_sampled[31] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES31
|
|
assign extc_in [30] = rgpio_nec [30] ? nextc_sampled[30] : pextc_sampled[30] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES30
|
|
assign extc_in [29] = rgpio_nec [29] ? nextc_sampled[29] : pextc_sampled[29] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES29
|
|
assign extc_in [28] = rgpio_nec [28] ? nextc_sampled[28] : pextc_sampled[28] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES28
|
|
assign extc_in [27] = rgpio_nec [27] ? nextc_sampled[27] : pextc_sampled[27] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES27
|
|
assign extc_in [26] = rgpio_nec [26] ? nextc_sampled[26] : pextc_sampled[26] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES26
|
|
assign extc_in [25] = rgpio_nec [25] ? nextc_sampled[25] : pextc_sampled[25] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES25
|
|
assign extc_in [24] = rgpio_nec [24] ? nextc_sampled[24] : pextc_sampled[24] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES24
|
|
assign extc_in [23] = rgpio_nec [23] ? nextc_sampled[23] : pextc_sampled[23] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES23
|
|
assign extc_in [22] = rgpio_nec [22] ? nextc_sampled[22] : pextc_sampled[22] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES22
|
|
assign extc_in [21] = rgpio_nec [21] ? nextc_sampled[21] : pextc_sampled[21] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES21
|
`ifdef GPIO_SYNC_IN_CLK_WB
|
assign extc_in [20] = rgpio_nec [20] ? nextc_sampled[20] : pextc_sampled[20] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES20
|
|
assign extc_in [19] = rgpio_nec [19] ? nextc_sampled[19] : pextc_sampled[19] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES19
|
reg [gw-1:0] syn_extc ,
|
assign extc_in [18] = rgpio_nec [18] ? nextc_sampled[18] : pextc_sampled[18] ;
|
extc_s ;
|
`endif
|
|
|
|
`ifdef GPIO_LINES18
|
|
assign extc_in [17] = rgpio_nec [17] ? nextc_sampled[17] : pextc_sampled[17] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES17
|
|
assign extc_in [16] = rgpio_nec [16] ? nextc_sampled[16] : pextc_sampled[16] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES16
|
|
assign extc_in [15] = rgpio_nec [15] ? nextc_sampled[15] : pextc_sampled[15] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES15
|
|
assign extc_in [14] = rgpio_nec [14] ? nextc_sampled[14] : pextc_sampled[14] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES14
|
|
assign extc_in [13] = rgpio_nec [13] ? nextc_sampled[13] : pextc_sampled[13] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES13
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
assign extc_in [12] = rgpio_nec [12] ? nextc_sampled[12] : pextc_sampled[12] ;
|
if (wb_rst_i) begin
|
`endif
|
syn_extc <= #1 {gw{1'b0}};
|
|
extc_s <= #1 {gw{1'b0}};
|
`ifdef GPIO_LINES12
|
end else begin
|
assign extc_in [11] = rgpio_nec [11] ? nextc_sampled[11] : pextc_sampled[11] ;
|
syn_extc <= #1 extc_in ;
|
`endif
|
extc_s <= #1 syn_extc;
|
|
end
|
`ifdef GPIO_LINES11
|
|
assign extc_in [10] = rgpio_nec [10] ? nextc_sampled[10] : pextc_sampled[10] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES10
|
|
assign extc_in [9] = rgpio_nec [9] ? nextc_sampled[9] : pextc_sampled[9] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES9
|
|
assign extc_in [8] = rgpio_nec [8] ? nextc_sampled[8] : pextc_sampled[8] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES8
|
|
assign extc_in [7] = rgpio_nec [7] ? nextc_sampled[7] : pextc_sampled[7] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES7
|
`else
|
assign extc_in [6] = rgpio_nec [6] ? nextc_sampled[6] : pextc_sampled[6] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES6
|
wire [gw-1:0] extc_s ;
|
assign extc_in [5] = rgpio_nec [5] ? nextc_sampled[5] : pextc_sampled[5] ;
|
assign extc_s = syn_extc ;
|
`endif
|
|
|
|
`ifdef GPIO_LINES5
|
`endif // GPIO_SYNC_IN_CLK_WB
|
assign extc_in [4] = rgpio_nec [4] ? nextc_sampled[4] : pextc_sampled[4] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES4
|
`ifdef GPIO_SYNC_IN_CLK
|
assign extc_in [3] = rgpio_nec [3] ? nextc_sampled[3] : pextc_sampled[3] ;
|
reg [gw-1:0] syn_pclk ,
|
`endif
|
ext_pad_spc ;
|
|
|
`ifdef GPIO_LINES3
|
always @(posedge clk_pad_i or posedge wb_rst_i)
|
assign extc_in [2] = rgpio_nec [2] ? nextc_sampled[2] : pextc_sampled[2] ;
|
if (wb_rst_i) begin
|
`endif
|
syn_pclk <= #1 {gw{1'b0}} ;
|
|
ext_pad_spc <= #1 {gw{1'b0}} ;
|
|
end else begin
|
|
syn_pclk <= #1 ext_pad_i ;
|
|
ext_pad_spc <= #1 syn_pclk ;
|
|
end
|
|
|
`ifdef GPIO_LINES2
|
`else
|
assign extc_in [1] = rgpio_nec [1] ? nextc_sampled[1] : pextc_sampled[1] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES1
|
wire [gw-1:0] ext_pad_spc ;
|
assign extc_in [0] = rgpio_nec [0] ? nextc_sampled[0] : pextc_sampled[0] ;
|
assign ext_pad_spc = ext_pad_i ;
|
`endif
|
|
|
|
`endif
|
`endif // GPIO_SYNC_IN_CLK
|
|
|
//
|
always @(posedge clk_pad_i or posedge wb_rst_i)
|
// Latch using posedge external clock
|
if (wb_rst_i) begin
|
//
|
pextc_sampled <= #1 {gw{1'b0}};
|
|
end else begin
|
|
pextc_sampled <= #1 ext_pad_spc ;
|
|
end
|
|
|
`ifdef GPIO_LINES32
|
|
always @(posedge pext_clk[31] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[31] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[31] <= #1 ext_pad_i[31];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES31
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
always @(posedge pext_clk[30] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[30] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[30] <= #1 ext_pad_i[30];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES30
|
`ifdef GPIO_NO_CLKPAD_LOGIC
|
always @(posedge pext_clk[29] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[29] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[29] <= #1 ext_pad_i[29];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES29
|
assign extc_in = pextc_sampled;
|
always @(posedge pext_clk[28] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[28] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[28] <= #1 ext_pad_i[28];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES28
|
`else
|
always @(posedge pext_clk[27] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[27] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[27] <= #1 ext_pad_i[27];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES27
|
wire clk_n;
|
always @(posedge pext_clk[26] or posedge wb_rst_i)
|
assign clk_n = !clk_pad_i;
|
if (wb_rst_i)
|
|
pextc_sampled[26] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[26] <= #1 ext_pad_i[26];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES26
|
`ifdef GPIO_SYNC_IN_CLK
|
always @(posedge pext_clk[25] or posedge wb_rst_i)
|
reg [gw-1:0] syn_nclk ,
|
if (wb_rst_i)
|
ext_pad_snc ;
|
pextc_sampled[25] <= #1 1'b0;
|
|
else
|
always @(posedge clk_n or posedge wb_rst_i)
|
pextc_sampled[25] <= #1 ext_pad_i[25];
|
if (wb_rst_i) begin
|
`endif
|
syn_nclk <= #1 {gw{1'b0}} ;
|
|
ext_pad_snc <= #1 {gw{1'b0}} ;
|
|
end else begin
|
|
syn_nclk <= #1 ext_pad_i ;
|
|
ext_pad_snc <= #1 syn_nclk ;
|
|
end
|
|
|
`ifdef GPIO_LINES25
|
`else
|
always @(posedge pext_clk[24] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[24] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[24] <= #1 ext_pad_i[24];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES24
|
wire [gw-1:0] ext_pad_snc ;
|
always @(posedge pext_clk[23] or posedge wb_rst_i)
|
assign ext_pad_snc = ext_pad_i ;
|
if (wb_rst_i)
|
|
pextc_sampled[23] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[23] <= #1 ext_pad_i[23];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES23
|
`endif // GPIO_SYNC_IN_CLK
|
always @(posedge pext_clk[22] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[22] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[22] <= #1 ext_pad_i[22];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES22
|
always @(posedge clk_n or posedge wb_rst_i)
|
always @(posedge pext_clk[21] or posedge wb_rst_i)
|
if (wb_rst_i) begin
|
if (wb_rst_i)
|
nextc_sampled <= #1 {gw{1'b0}};
|
pextc_sampled[21] <= #1 1'b0;
|
end else begin
|
else
|
nextc_sampled <= #1 ext_pad_snc ;
|
pextc_sampled[21] <= #1 ext_pad_i[21];
|
end
|
`endif
|
|
|
|
`ifdef GPIO_LINES21
|
|
always @(posedge pext_clk[20] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[20] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[20] <= #1 ext_pad_i[20];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES20
|
assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;
|
always @(posedge pext_clk[19] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[19] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[19] <= #1 ext_pad_i[19];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES19
|
`endif // GPIO_NO_CLKPAD_LOGIC
|
always @(posedge pext_clk[18] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[18] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[18] <= #1 ext_pad_i[18];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES18
|
|
always @(posedge pext_clk[17] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[17] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[17] <= #1 ext_pad_i[17];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES17
|
`else
|
always @(posedge pext_clk[16] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[16] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[16] <= #1 ext_pad_i[16];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES16
|
`ifdef GPIO_SYNC_IN_CLK
|
always @(posedge pext_clk[15] or posedge wb_rst_i)
|
reg [gw-1:0] syn_nclk ,
|
if (wb_rst_i)
|
ext_pad_snc ;
|
pextc_sampled[15] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[15] <= #1 ext_pad_i[15];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES15
|
always @(negedge clk_n or posedge wb_rst_i)
|
always @(posedge pext_clk[14] or posedge wb_rst_i)
|
if (wb_rst_i) begin
|
if (wb_rst_i)
|
syn_nclk <= #1 {gw{1'b0}} ;
|
pextc_sampled[14] <= #1 1'b0;
|
ext_pad_snc <= #1 {gw{1'b0}} ;
|
else
|
end else begin
|
pextc_sampled[14] <= #1 ext_pad_i[14];
|
syn_nclk <= #1 ext_pad_i ;
|
`endif
|
ext_pad_snc <= #1 syn_nclk ;
|
|
end
|
|
|
`ifdef GPIO_LINES14
|
`else
|
always @(posedge pext_clk[13] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[13] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[13] <= #1 ext_pad_i[13];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES13
|
wire [gw-1:0] ext_pad_snc ;
|
always @(posedge pext_clk[12] or posedge wb_rst_i)
|
assign ext_pad_snc = ext_pad_i ;
|
if (wb_rst_i)
|
|
pextc_sampled[12] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[12] <= #1 ext_pad_i[12];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES12
|
`endif // GPIO_SYNC_IN_CLK
|
always @(posedge pext_clk[11] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[11] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[11] <= #1 ext_pad_i[11];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES11
|
always @(negedge clk_pad_i or posedge wb_rst_i)
|
always @(posedge pext_clk[10] or posedge wb_rst_i)
|
if (wb_rst_i) begin
|
if (wb_rst_i)
|
nextc_sampled <= #1 {gw{1'b0}};
|
pextc_sampled[10] <= #1 1'b0;
|
end else begin
|
else
|
nextc_sampled <= #1 ext_pad_snc ;
|
pextc_sampled[10] <= #1 ext_pad_i[10];
|
end
|
`endif
|
|
|
|
`ifdef GPIO_LINES10
|
assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;
|
always @(posedge pext_clk[9] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[9] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[9] <= #1 ext_pad_i[9];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES9
|
`endif // GPIO_NO_NEGEDGE_FLOPS
|
always @(posedge pext_clk[8] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[8] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[8] <= #1 ext_pad_i[8];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES8
|
assign in_muxed = (rgpio_eclk & extc_s) | (~rgpio_eclk & ext_pad_s) ;
|
always @(posedge pext_clk[7] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[7] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[7] <= #1 ext_pad_i[7];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES7
|
|
always @(posedge pext_clk[6] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[6] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[6] <= #1 ext_pad_i[6];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES6
|
`endif // GPIO_SYNC_CLK_WB
|
always @(posedge pext_clk[5] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[5] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[5] <= #1 ext_pad_i[5];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES5
|
|
always @(posedge pext_clk[4] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[4] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[4] <= #1 ext_pad_i[4];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES4
|
`else
|
always @(posedge pext_clk[3] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[3] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[3] <= #1 ext_pad_i[3];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES3
|
assign in_muxed = ext_pad_s ;
|
always @(posedge pext_clk[2] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[2] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[2] <= #1 ext_pad_i[2];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES2
|
`endif // GPIO_CLKPAD
|
always @(posedge pext_clk[1] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[1] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[1] <= #1 ext_pad_i[1];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES1
|
|
always @(posedge pext_clk[0] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[0] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[0] <= #1 ext_pad_i[0];
|
|
`endif
|
|
|
|
//
|
|
// Latch using negedge external clock
|
|
//
|
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
|
`else
|
|
always @(negedge clk_pad_i or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
nextc_sampled <= #1 {gw{1'b0}};
|
|
else
|
|
nextc_sampled <= #1 ext_pad_i;
|
|
`endif
|
|
|
|
//
|
//
|
// Mux all registers when doing a read of GPIO registers
|
// Mux all registers when doing a read of GPIO registers
|
//
|
//
|
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
|
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
|
| Line 1513... |
Line 1059... |
if (wb_rst_i)
|
if (wb_rst_i)
|
rgpio_ints <= #1 {gw{1'b0}};
|
rgpio_ints <= #1 {gw{1'b0}};
|
else if (rgpio_ints_sel && wb_we_i)
|
else if (rgpio_ints_sel && wb_we_i)
|
rgpio_ints <= #1 wb_dat_i[gw-1:0];
|
rgpio_ints <= #1 wb_dat_i[gw-1:0];
|
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
|
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
|
rgpio_ints <= #1 (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte);
|
rgpio_ints <= #1 (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
|
`else
|
`else
|
assign rgpio_ints = (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte);
|
assign rgpio_ints = (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
|
`endif
|
`endif
|
|
|
//
|
//
|
// Generate interrupt request
|
// Generate interrupt request
|
//
|
//
|
| Line 1534... |
Line 1080... |
wb_inta_o <= #1 1'b0;
|
wb_inta_o <= #1 1'b0;
|
else
|
else
|
wb_inta_o <= #1 wb_inta;
|
wb_inta_o <= #1 wb_inta;
|
`else
|
`else
|
assign wb_inta_o = wb_inta;
|
assign wb_inta_o = wb_inta;
|
`endif
|
`endif // GPIO_REGISTERED_WB_OUTPUTS
|
|
|
//
|
//
|
// Output enables are RGPIO_OE bits
|
// Output enables are RGPIO_OE bits
|
//
|
//
|
assign ext_padoe_o = rgpio_oe;
|
assign ext_padoe_o = rgpio_oe;
|
|
|
//
|
//
|
// Generate GPIO outputs
|
// Generate GPIO outputs
|
//
|
//
|
|
`ifdef GPIO_AUX_IMPLEMENT
|
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
|
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
|
|
`else
|
|
assign out_pad = rgpio_out ;
|
|
`endif // GPIO_AUX_IMPLEMENT
|
|
|
//
|
//
|
// Optional registration of GPIO outputs
|
// Optional registration of GPIO outputs
|
//
|
//
|
`ifdef GPIO_REGISTERED_IO_OUTPUTS
|
`ifdef GPIO_REGISTERED_IO_OUTPUTS
|
| Line 1557... |
Line 1107... |
ext_pad_o <= #1 {gw{1'b0}};
|
ext_pad_o <= #1 {gw{1'b0}};
|
else
|
else
|
ext_pad_o <= #1 out_pad;
|
ext_pad_o <= #1 out_pad;
|
`else
|
`else
|
assign ext_pad_o = out_pad;
|
assign ext_pad_o = out_pad;
|
`endif
|
`endif // GPIO_REGISTERED_IO_OUTPUTS
|
|
|
|
|
`else
|
`else
|
|
|
//
|
//
|
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
|
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
|
| Line 1576... |
Line 1127... |
//
|
//
|
// Read GPIO registers
|
// Read GPIO registers
|
//
|
//
|
assign wb_dat_o = {dw{1'b0}};
|
assign wb_dat_o = {dw{1'b0}};
|
|
|
`endif
|
`endif // GPIO_IMPLEMENTED
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
