| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/11/15 02:24:37 lampret
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// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
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//
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// Revision 1.1 2001/09/18 18:49:07 lampret
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// Revision 1.1 2001/09/18 18:49:07 lampret
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// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
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// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
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//
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//
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// Revision 1.1 2001/08/21 21:39:28 lampret
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// Revision 1.1 2001/08/21 21:39:28 lampret
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// Changed directory structure, port names and drfines.
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// Changed directory structure, port names and drfines.
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| Line 176... |
Line 179... |
`define GPIO_RGPIO_OE 3'h2 // Address 0x08
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`define GPIO_RGPIO_OE 3'h2 // Address 0x08
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`define GPIO_RGPIO_INTE 3'h3 // Address 0x0c
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`define GPIO_RGPIO_INTE 3'h3 // Address 0x0c
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`define GPIO_RGPIO_PTRIG 3'h4 // Address 0x10
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`define GPIO_RGPIO_PTRIG 3'h4 // Address 0x10
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`define GPIO_RGPIO_AUX 3'h5 // Address 0x14
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`define GPIO_RGPIO_AUX 3'h5 // Address 0x14
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`define GPIO_RGPIO_CTRL 3'h6 // Address 0x18
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`define GPIO_RGPIO_CTRL 3'h6 // Address 0x18
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`define GPIO_RGPIO_INTS 3'h7 // Address 0x1c
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//
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//
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// Default values for unimplemented GPIO registers
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// Default values for unimplemented GPIO registers
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//
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//
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`define GPIO_DEF_RGPIO_IN `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_IN `GPIO_IOS'h0
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Line 201... |
// bit 0 to bit 3 in the following order: ECLK, NEC, INTE, INT
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// bit 0 to bit 3 in the following order: ECLK, NEC, INTE, INT
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//
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//
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`define GPIO_RGPIO_CTRL_ECLK 0
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`define GPIO_RGPIO_CTRL_ECLK 0
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`define GPIO_RGPIO_CTRL_NEC 1
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`define GPIO_RGPIO_CTRL_NEC 1
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`define GPIO_RGPIO_CTRL_INTE 2
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`define GPIO_RGPIO_CTRL_INTE 2
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`define GPIO_RGPIO_CTRL_INT 3
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`define GPIO_RGPIO_CTRL_INTS 3
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No newline at end of file
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No newline at end of file
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