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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/09/18 18:49:07 lampret
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// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
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//
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// Revision 1.1 2001/08/21 21:39:28 lampret
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// Revision 1.1 2001/08/21 21:39:28 lampret
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// Changed directory structure, port names and drfines.
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// Changed directory structure, port names and drfines.
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//
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//
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// Revision 1.2 2001/07/14 20:39:26 lampret
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// Revision 1.2 2001/07/14 20:39:26 lampret
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// Better configurability.
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// Better configurability.
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Line 193... |
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
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// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
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//
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//
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assign wb_ack_o = wb_cyc_i & wb_stb_i & !wb_err_o;
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assign wb_ack_o = wb_cyc_i & wb_stb_i & !wb_err_o;
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`ifdef GPIO_FULL_DECODE
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`ifdef GPIO_FULL_DECODE
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`ifdef GPIO_STRICT_32BIT_ACCESS
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`ifdef GPIO_STRICT_32BIT_ACCESS
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assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding | (wb_sel_i != 4'b1111);
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assign wb_err_o = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
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`else
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`else
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assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding;
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assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding;
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`endif
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`endif
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`else
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`else
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`ifdef GPIO_STRICT_32BIT_ACCESS
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`ifdef GPIO_STRICT_32BIT_ACCESS
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assign wb_err_o = (wb_sel_i != 4'b1111);
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assign wb_err_o = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
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`else
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`else
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assign wb_err_o = 1'b0;
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assign wb_err_o = 1'b0;
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`endif
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`endif
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`endif
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`endif
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Line 335... |
rgpio_ptrig or rgpio_aux or rgpio_ctrl)
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rgpio_ptrig or rgpio_aux or rgpio_ctrl)
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case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
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case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
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`ifdef GPIO_READREGS
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`ifdef GPIO_READREGS
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`GPIO_RGPIO_OUT: begin
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`GPIO_RGPIO_OUT: begin
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_out};
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_out};
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// wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};
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end
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end
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`GPIO_RGPIO_OE: begin
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`GPIO_RGPIO_OE: begin
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_oe};
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_oe};
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// wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};
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end
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end
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`GPIO_RGPIO_INTE: begin
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`GPIO_RGPIO_INTE: begin
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_inte};
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_inte};
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// wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};
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end
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end
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`GPIO_RGPIO_PTRIG: begin
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`GPIO_RGPIO_PTRIG: begin
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_ptrig};
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_ptrig};
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// wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};
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end
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end
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`GPIO_RGPIO_AUX: begin
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`GPIO_RGPIO_AUX: begin
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_aux};
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_aux};
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// wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};
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end
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end
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`GPIO_RGPIO_CTRL: begin
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`GPIO_RGPIO_CTRL: begin
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wb_dat_o[3:0] <= rgpio_ctrl;
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wb_dat_o[3:0] <= rgpio_ctrl;
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wb_dat_o[dw-1:4] <= {dw-4{1'b0}};
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wb_dat_o[dw-1:4] <= {dw-4{1'b0}};
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end
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end
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`endif
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`endif
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default: begin
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default: begin
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_in};
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_in};
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// wb_dat_o[dw-1:gw] <= {dw-gw{1'b0}};
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end
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end
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endcase
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endcase
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//
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//
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// Generate interrupt request
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// Generate interrupt request
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