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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2001/12/12 20:35:53 lampret
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// Fixing style.
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//
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// Revision 1.4 2001/12/12 07:12:58 lampret
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// Revision 1.4 2001/12/12 07:12:58 lampret
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// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
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// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
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//
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//
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// Revision 1.3 2001/11/15 02:24:37 lampret
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// Revision 1.3 2001/11/15 02:24:37 lampret
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// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
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// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
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| Line 180... |
Line 183... |
`else
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`else
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wire [3:0] rgpio_ctrl; // No register
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wire [3:0] rgpio_ctrl; // No register
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`endif
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`endif
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//
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//
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// GPIO Interrupt Status Register (or no register)
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//
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`ifdef GPIO_RGPIO_INTS
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reg [gw-1:0] rgpio_ints; // RGPIO_INTS register
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`else
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wire [gw-1:0] rgpio_ints; // No register
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`endif
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//
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// Internal wires & regs
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// Internal wires & regs
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//
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//
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wire rgpio_out_sel; // RGPIO_OUT select
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wire rgpio_out_sel; // RGPIO_OUT select
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wire rgpio_oe_sel; // RGPIO_OE select
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wire rgpio_oe_sel; // RGPIO_OE select
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wire rgpio_inte_sel; // RGPIO_INTE select
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wire rgpio_inte_sel; // RGPIO_INTE select
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wire rgpio_ptrig_sel;// RGPIO_PTRIG select
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wire rgpio_ptrig_sel;// RGPIO_PTRIG select
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wire rgpio_aux_sel; // RGPIO_AUX select
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wire rgpio_aux_sel; // RGPIO_AUX select
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wire rgpio_ctrl_sel; // RGPIO_CTRL select
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wire rgpio_ctrl_sel; // RGPIO_CTRL select
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wire rgpio_ints_sel; // RGPIO_INTS select
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wire latch_clk; // Latch clock
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wire latch_clk; // Latch clock
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wire full_decoding; // Full address decoding qualification
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wire full_decoding; // Full address decoding qualification
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wire [gw-1:0] in_muxed; // Muxed inputs
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wire [gw-1:0] in_muxed; // Muxed inputs
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wire wb_ack; // WB Acknowledge
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wire wb_ack; // WB Acknowledge
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wire wb_err; // WB Error
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wire wb_err; // WB Error
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| Line 287... |
Line 300... |
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
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assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
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assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
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assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
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assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
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assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
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assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
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assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
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assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
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assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
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assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
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//
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//
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// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
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// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
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//
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//
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`ifdef GPIO_RGPIO_CTRL
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`ifdef GPIO_RGPIO_CTRL
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| Line 298... |
Line 312... |
if (wb_rst_i)
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if (wb_rst_i)
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rgpio_ctrl <= #1 4'b0;
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rgpio_ctrl <= #1 4'b0;
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else if (rgpio_ctrl_sel && wb_we_i)
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else if (rgpio_ctrl_sel && wb_we_i)
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rgpio_ctrl <= #1 wb_dat_i[3:0];
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rgpio_ctrl <= #1 wb_dat_i[3:0];
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else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
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else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
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rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] | wb_inta_o;
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rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
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`else
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`else
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assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1
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assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1
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`endif
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`endif
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//
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//
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| Line 453... |
Line 467... |
`GPIO_RGPIO_CTRL: begin
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`GPIO_RGPIO_CTRL: begin
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wb_dat[3:0] = rgpio_ctrl;
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wb_dat[3:0] = rgpio_ctrl;
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wb_dat[dw-1:4] = {dw-4{1'b0}};
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wb_dat[dw-1:4] = {dw-4{1'b0}};
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end
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end
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`endif
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`endif
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`GPIO_RGPIO_INTS: begin
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wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ints};
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end
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default: begin
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default: begin
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wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_in};
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wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_in};
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end
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end
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endcase
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endcase
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| Line 472... |
Line 489... |
`else
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`else
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assign wb_dat_o = wb_dat;
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assign wb_dat_o = wb_dat;
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`endif
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`endif
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//
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//
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// RGPIO_INTS
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//
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`ifdef GPIO_RGPIO_INTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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rgpio_ints <= #1 {gw{1'b0}};
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else if (rgpio_ints_sel && wb_we_i)
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rgpio_ints <= #1 wb_dat_i[gw-1:0];
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else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
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rgpio_ints <= #1 rgpio_ints | (in_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
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`else
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assign rgpio_ints = (in_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
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`endif
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//
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// Generate interrupt request
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// Generate interrupt request
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//
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//
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assign wb_inta = ((in_pad_i ^ ~rgpio_ptrig) & rgpio_inte) ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
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assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
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//
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//
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// Optional registration of WB interrupt
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// Optional registration of WB interrupt
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//
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//
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`ifdef GPIO_REGISTERED_WB_OUTPUTS
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`ifdef GPIO_REGISTERED_WB_OUTPUTS
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