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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2002/03/09 03:43:27 lampret
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// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)
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//
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// Revision 1.8 2002/01/14 19:06:28 lampret
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// Revision 1.8 2002/01/14 19:06:28 lampret
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// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.
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// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.
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//
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//
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// Revision 1.7 2001/12/25 17:21:21 lampret
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// Revision 1.7 2001/12/25 17:21:21 lampret
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// Fixed two typos.
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// Fixed two typos.
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| Line 92... |
Line 95... |
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// Auxiliary inputs interface
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// Auxiliary inputs interface
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aux_i,
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aux_i,
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// External GPIO Interface
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// External GPIO Interface
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in_pad_i, ext_clk_pad_i, out_pad_o, oen_padoen_o
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ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o
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);
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);
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parameter dw = 32;
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parameter dw = 32;
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parameter aw = `GPIO_ADDRHH+1;
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parameter aw = `GPIO_ADDRHH+1;
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parameter gw = `GPIO_IOS;
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parameter gw = `GPIO_IOS;
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Line 124... |
input [gw-1:0] aux_i; // Auxiliary inputs
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input [gw-1:0] aux_i; // Auxiliary inputs
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//
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//
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// External GPIO Interface
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// External GPIO Interface
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//
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//
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input [gw-1:0] in_pad_i; // GPIO Inputs
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input [gw-1:0] ext_pad_i; // GPIO Inputs
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input ext_clk_pad_i; // GPIO Eclk
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input clk_pad_i; // GPIO Eclk
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output [gw-1:0] out_pad_o; // GPIO Outputs
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output [gw-1:0] ext_pad_o; // GPIO Outputs
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output [gw-1:0] oen_padoen_o; // GPIO output drivers enables
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output [gw-1:0] ext_padoen_o; // GPIO output drivers enables
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`ifdef GPIO_IMPLEMENTED
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`ifdef GPIO_IMPLEMENTED
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//
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//
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// GPIO Input Register (or no register)
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// GPIO Input Register (or no register)
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Line 228... |
reg wb_inta_o; // WB Interrupt
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reg wb_inta_o; // WB Interrupt
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reg [dw-1:0] wb_dat_o; // WB Data out
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reg [dw-1:0] wb_dat_o; // WB Data out
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`endif
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`endif
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wire [gw-1:0] out_pad; // GPIO Outputs
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wire [gw-1:0] out_pad; // GPIO Outputs
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`ifdef GPIO_REGISTERED_IO_OUTPUTS
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`ifdef GPIO_REGISTERED_IO_OUTPUTS
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reg [gw-1:0] out_pad_o; // GPIO Outputs
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reg [gw-1:0] ext_pad_o; // GPIO Outputs
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`endif
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`endif
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wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock
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wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock
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wire pext_clk; // External clock for posedge flops
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wire pext_clk; // External clock for posedge flops
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reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs
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reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs
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`ifdef GPIO_NO_NEGEDGE_FLOPS
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`ifdef GPIO_NO_NEGEDGE_FLOPS
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Line 410... |
`endif
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`endif
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//
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//
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// Mux inputs directly from input pads with inputs sampled by external clock
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// Mux inputs directly from input pads with inputs sampled by external clock
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//
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//
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assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : in_pad_i;
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assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
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//
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//
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// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
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// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
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// If negedge flops are allowed, pext_clk only clocks posedge flops.
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// If negedge flops are allowed, pext_clk only clocks posedge flops.
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//
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//
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`ifdef GPIO_NO_NEGEDGE_FLOPS
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`ifdef GPIO_NO_NEGEDGE_FLOPS
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assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~ext_clk_pad_i : ext_clk_pad_i;
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assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
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`else
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`else
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assign pext_clk = ext_clk_pad_i;
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assign pext_clk = clk_pad_i;
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`endif
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`endif
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//
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//
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// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
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// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
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//
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//
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//
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//
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always @(posedge pext_clk or posedge wb_rst_i)
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always @(posedge pext_clk or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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pextc_sampled <= #1 {gw{1'b0}};
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pextc_sampled <= #1 {gw{1'b0}};
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else
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else
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pextc_sampled <= #1 in_pad_i;
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pextc_sampled <= #1 ext_pad_i;
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//
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//
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// Latch using negedge external clock
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// Latch using negedge external clock
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//
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//
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`ifdef GPIO_NO_NEGEDGE_FLOPS
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`ifdef GPIO_NO_NEGEDGE_FLOPS
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`else
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`else
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always @(negedge ext_clk_pad_i or posedge wb_rst_i)
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always @(negedge clk_pad_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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nextc_sampled <= #1 {gw{1'b0}};
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nextc_sampled <= #1 {gw{1'b0}};
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else
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else
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nextc_sampled <= #1 in_pad_i;
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nextc_sampled <= #1 ext_pad_i;
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`endif
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`endif
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//
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//
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// Mux all registers when doing a read of GPIO registers
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// Mux all registers when doing a read of GPIO registers
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//
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//
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Line 509... |
always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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rgpio_ints <= #1 {gw{1'b0}};
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rgpio_ints <= #1 {gw{1'b0}};
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else if (rgpio_ints_sel && wb_we_i)
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else if (rgpio_ints_sel && wb_we_i)
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rgpio_ints <= #1 wb_dat_i[gw-1:0];
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rgpio_ints <= #1 wb_dat_i[gw-1:0];
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else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] && rgpio_in != in_pad_i)
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else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] && rgpio_in != ext_pad_i)
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rgpio_ints <= #1 (rgpio_ints | (in_pad_i ^ ~rgpio_ptrig) & rgpio_inte);
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rgpio_ints <= #1 (rgpio_ints | (ext_pad_i ^ ~rgpio_ptrig) & rgpio_inte);
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`else
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`else
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assign rgpio_ints = (in_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
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assign rgpio_ints = (ext_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
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`endif
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`endif
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//
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//
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// Generate interrupt request
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// Generate interrupt request
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//
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//
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Line 536... |
`endif
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`endif
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//
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//
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// Output enables are RGPIO_OE bits
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// Output enables are RGPIO_OE bits
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//
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//
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assign oen_padoen_o = rgpio_oe;
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assign ext_padoen_o = rgpio_oe;
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//
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//
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// Generate GPIO outputs
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// Generate GPIO outputs
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//
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//
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assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
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assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
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Line 549... |
// Optional registration of GPIO outputs
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// Optional registration of GPIO outputs
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//
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//
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`ifdef GPIO_REGISTERED_IO_OUTPUTS
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`ifdef GPIO_REGISTERED_IO_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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out_pad_o <= #1 {gw{1'b0}};
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ext_pad_o <= #1 {gw{1'b0}};
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else
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else
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out_pad_o <= #1 out_pad;
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ext_pad_o <= #1 out_pad;
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`else
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`else
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assign out_pad_o = out_pad;
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assign ext_pad_o = out_pad;
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`endif
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`endif
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`else
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`else
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//
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//
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Line 565... |
// is cleared and WISHBONE transfers complete with errors
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// is cleared and WISHBONE transfers complete with errors
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//
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//
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assign wb_inta_o = 1'b0;
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assign wb_inta_o = 1'b0;
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assign wb_ack_o = 1'b0;
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assign wb_ack_o = 1'b0;
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assign wb_err_o = wb_cyc_i & wb_stb_i;
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assign wb_err_o = wb_cyc_i & wb_stb_i;
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assign oen_padoen_o = {gw{1'b1}};
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assign ext_padoen_o = {gw{1'b1}};
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assign out_pad_o = {gw{1'b0}};
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assign ext_pad_o = {gw{1'b0}};
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//
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//
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// Read GPIO registers
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// Read GPIO registers
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//
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//
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assign wb_dat_o = {dw{1'b0}};
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assign wb_dat_o = {dw{1'b0}};
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