| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
|
|
// Revision 1.3 2002/03/13 20:56:16 lampret
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// Removed zero padding as per Avi Shamli suggestion.
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//
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// Revision 1.2 2001/09/18 15:43:28 lampret
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// Revision 1.2 2001/09/18 15:43:28 lampret
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// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.
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// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.
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//
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//
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// Revision 1.1 2001/08/21 21:39:27 lampret
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// Revision 1.1 2001/08/21 21:39:27 lampret
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// Changed directory structure, port names and drfines.
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// Changed directory structure, port names and drfines.
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| Line 61... |
Line 64... |
`include "timescale.v"
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`include "timescale.v"
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`include "gpio_defines.v"
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`include "gpio_defines.v"
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|
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module tb_top;
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module tb_top;
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|
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parameter aw = 32;
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parameter aw = `GPIO_ADDRHH+1 ;
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parameter dw = 32;
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parameter dw = 32;
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parameter gw = `GPIO_IOS;
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parameter gw = `GPIO_IOS;
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|
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//
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//
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// Interconnect wires
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// Interconnect wires
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| Line 84... |
Line 87... |
wire [gw-1:0] gpio_aux; // GPIO auxiliary signals
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wire [gw-1:0] gpio_aux; // GPIO auxiliary signals
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wire [gw-1:0] gpio_in; // GPIO inputs
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wire [gw-1:0] gpio_in; // GPIO inputs
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wire gpio_eclk; // GPIO external clock
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wire gpio_eclk; // GPIO external clock
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wire [gw-1:0] gpio_out; // GPIO outputs
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wire [gw-1:0] gpio_out; // GPIO outputs
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wire [gw-1:0] gpio_oen; // GPIO output enables
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wire [gw-1:0] gpio_oen; // GPIO output enables
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wire [ 3 : 0 ] tag_o ;
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|
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//
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//
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// Instantiation of Clock/Reset Generator
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// Instantiation of Clock/Reset Generator
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//
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//
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clkrst clkrst(
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clkrst clkrst(
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| Line 111... |
Line 115... |
.WE_O(we),
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.WE_O(we),
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.STB_O(stb),
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.STB_O(stb),
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.DAT_I(dat_m),
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.DAT_I(dat_m),
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.ACK_I(ack),
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.ACK_I(ack),
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.ERR_I(err),
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.ERR_I(err),
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.RTY_I(0),
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.RTY_I(1'b0),
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.TAG_I(4'b0)
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.TAG_I(4'b0),
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.TAG_O ( tag_o )
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);
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);
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|
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//
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//
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// Instantiation of PTC core
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// Instantiation of PTC core
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//
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//
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gpio_top gpio_top(
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gpio_top gpio_top(
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// WISHBONE Interface
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// WISHBONE Interface
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.wb_clk_i(clk),
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.wb_clk_i(clk),
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.wb_rst_i(rst),
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.wb_rst_i(rst),
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.wb_cyc_i(cyc),
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.wb_cyc_i(cyc),
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.wb_adr_i(adr[15:0]),
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.wb_adr_i(adr),
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.wb_dat_i(dat_ptc),
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.wb_dat_i(dat_ptc),
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.wb_sel_i(sel),
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.wb_sel_i(sel),
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.wb_we_i(we),
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.wb_we_i(we),
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.wb_stb_i(stb),
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.wb_stb_i(stb),
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.wb_dat_o(dat_m),
|
.wb_dat_o(dat_m),
|
