| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/10/31 02:26:51 lampret
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// Fixed wb_err_o.
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//
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// Revision 1.1 2001/09/18 18:49:07 lampret
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// Revision 1.1 2001/09/18 18:49:07 lampret
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// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
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// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
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//
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//
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// Revision 1.1 2001/08/21 21:39:28 lampret
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// Revision 1.1 2001/08/21 21:39:28 lampret
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// Changed directory structure, port names and drfines.
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// Changed directory structure, port names and drfines.
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| Line 182... |
Line 185... |
wire rgpio_ptrig_sel;// RGPIO_PTRIG select
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wire rgpio_ptrig_sel;// RGPIO_PTRIG select
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wire rgpio_aux_sel; // RGPIO_AUX select
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wire rgpio_aux_sel; // RGPIO_AUX select
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wire rgpio_ctrl_sel; // RGPIO_CTRL select
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wire rgpio_ctrl_sel; // RGPIO_CTRL select
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wire latch_clk; // Latch clock
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wire latch_clk; // Latch clock
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wire full_decoding; // Full address decoding qualification
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wire full_decoding; // Full address decoding qualification
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reg [dw-1:0] wb_dat_o; // Data out
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wire [gw-1:0] in_muxed; // Muxed inputs
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wire wb_ack; // WB Acknowledge
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wire wb_err; // WB Error
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wire wb_inta; // WB Interrupt
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reg [dw-1:0] wb_dat; // WB Data out
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`ifdef GPIO_REGISTERED_WB_OUTPUTS
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reg wb_ack_o; // WB Acknowledge
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reg wb_err_o; // WB Error
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reg wb_inta_o; // WB Interrupt
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reg [dw-1:0] wb_dat_o; // WB Data out
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`endif
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wire [gw-1:0] out_pad; // GPIO Outputs
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`ifdef GPIO_REGISTERED_IO_OUTPUTS
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reg [gw-1:0] out_pad_o; // GPIO Outputs
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`endif
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wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock
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wire pext_clk; // External clock for posedge flops
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reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs
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`ifdef GPIO_NO_NEGEDGE_FLOPS
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`else
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reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
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`endif
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//
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//
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// All WISHBONE transfer terminations are successful except when:
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// All WISHBONE transfer terminations are successful except when:
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// a) full address decoding is enabled and address doesn't match
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// a) full address decoding is enabled and address doesn't match
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// any of the GPIO registers
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// any of the GPIO registers
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// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
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// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
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//
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//
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assign wb_ack_o = wb_cyc_i & wb_stb_i & !wb_err_o;
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//
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// WB Acknowledge
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//
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assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
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//
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// Optional registration of WB Ack
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//
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`ifdef GPIO_REGISTERED_WB_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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wb_ack_o <= #1 1'b0;
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else
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wb_ack_o <= #1 wb_ack;
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`else
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assign wb_ack_o = wb_ack;
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`endif
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//
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// WB Error
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//
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`ifdef GPIO_FULL_DECODE
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`ifdef GPIO_FULL_DECODE
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`ifdef GPIO_STRICT_32BIT_ACCESS
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`ifdef GPIO_STRICT_32BIT_ACCESS
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assign wb_err_o = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
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assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
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`else
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`else
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assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding;
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assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
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`endif
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`endif
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`else
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`else
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`ifdef GPIO_STRICT_32BIT_ACCESS
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`ifdef GPIO_STRICT_32BIT_ACCESS
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assign wb_err_o = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
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assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
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`else
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`else
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assign wb_err_o = 1'b0;
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assign wb_err = 1'b0;
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`endif
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`endif
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`endif
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`endif
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//
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//
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// Latch clock is selected by RGPIO_CTRL[ECLK]. When it is set,
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// Optional registration of WB error
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// external clock is used.
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//
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//
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assign latch_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ?
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`ifdef GPIO_REGISTERED_WB_OUTPUTS
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ext_clk_pad_i ^ rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] : wb_clk_i;
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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wb_err_o <= #1 1'b0;
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else
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wb_err_o <= #1 wb_err;
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`else
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assign wb_err_o = wb_err;
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`endif
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//
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//
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// Full address decoder
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// Full address decoder
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//
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//
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`ifdef GPIO_FULL_DECODE
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`ifdef GPIO_FULL_DECODE
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| Line 258... |
Line 309... |
if (wb_rst_i)
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if (wb_rst_i)
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rgpio_out <= #1 {gw{1'b0}};
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rgpio_out <= #1 {gw{1'b0}};
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else if (rgpio_out_sel && wb_we_i)
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else if (rgpio_out_sel && wb_we_i)
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rgpio_out <= #1 wb_dat_i[gw-1:0];
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rgpio_out <= #1 wb_dat_i[gw-1:0];
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`else
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`else
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assign rgpio_out = `GPIO_DEF_RPGIO_OUT; // RGPIO_OUT = 0x0
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assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
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`endif
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`endif
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//
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//
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// Write to RGPIO_OE
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// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
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//
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//
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`ifdef GPIO_RGPIO_OE
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`ifdef GPIO_RGPIO_OE
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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rgpio_oe <= #1 {gw{1'b0}};
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rgpio_oe <= #1 {gw{1'b0}};
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else if (rgpio_oe_sel && wb_we_i)
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else if (rgpio_oe_sel && wb_we_i)
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rgpio_oe <= #1 wb_dat_i[gw-1:0];
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rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
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`else
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`else
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assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
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assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
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`endif
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`endif
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//
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//
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| Line 317... |
Line 368... |
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//
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//
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// Latch into RGPIO_IN
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// Latch into RGPIO_IN
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//
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//
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`ifdef GPIO_RGPIO_IN
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`ifdef GPIO_RGPIO_IN
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always @(posedge latch_clk or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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rgpio_in <= #1 {gw{1'b0}};
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rgpio_in <= #1 {gw{1'b0}};
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else
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else
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rgpio_in <= #1 in_pad_i;
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rgpio_in <= #1 in_muxed;
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`else
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assign rgpio_in = in_muxed;
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`endif
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//
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// Mux inputs directly from input pads with inputs sampled by external clock
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//
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assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : in_pad_i;
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//
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// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
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// If negedge flops are allowed, pext_clk only clocks posedge flops.
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//
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`ifdef GPIO_NO_NEGEDGE_FLOPS
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assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~ext_clk_pad_i : ext_clk_pad_i;
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`else
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assign pext_clk = ext_clk_pad_i;
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`endif
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//
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// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
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//
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`ifdef GPIO_NO_NEGEDGE_FLOPS
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assign extc_in = pextc_sampled;
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`else
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assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
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`endif
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//
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// Latch using posedge external clock
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//
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always @(posedge pext_clk or posedge wb_rst_i)
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if (wb_rst_i)
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pextc_sampled <= #1 {gw{1'b0}};
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else
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pextc_sampled <= #1 in_pad_i;
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//
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// Latch using negedge external clock
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//
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`ifdef GPIO_NO_NEGEDGE_FLOPS
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`else
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`else
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assign rgpio_in = in_pad_i;
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always @(negedge ext_clk_pad_i or posedge wb_rst_i)
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if (wb_rst_i)
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nextc_sampled <= #1 {gw{1'b0}};
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else
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nextc_sampled <= #1 in_pad_i;
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`endif
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`endif
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//
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//
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// Read GPIO registers
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// Mux all registers when doing a read of GPIO registers
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//
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//
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always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
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always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
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rgpio_ptrig or rgpio_aux or rgpio_ctrl)
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rgpio_ptrig or rgpio_aux or rgpio_ctrl)
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case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
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case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
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`ifdef GPIO_READREGS
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`ifdef GPIO_READREGS
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`GPIO_RGPIO_OUT: begin
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`GPIO_RGPIO_OUT: begin
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_out};
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wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_out};
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end
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end
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`GPIO_RGPIO_OE: begin
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`GPIO_RGPIO_OE: begin
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_oe};
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wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, ~rgpio_oe};
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end
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end
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`GPIO_RGPIO_INTE: begin
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`GPIO_RGPIO_INTE: begin
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_inte};
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wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_inte};
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end
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end
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`GPIO_RGPIO_PTRIG: begin
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`GPIO_RGPIO_PTRIG: begin
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_ptrig};
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wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_ptrig};
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end
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end
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`GPIO_RGPIO_AUX: begin
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`GPIO_RGPIO_AUX: begin
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_aux};
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wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_aux};
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end
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end
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`GPIO_RGPIO_CTRL: begin
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`GPIO_RGPIO_CTRL: begin
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wb_dat_o[3:0] <= rgpio_ctrl;
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wb_dat[3:0] <= rgpio_ctrl;
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wb_dat_o[dw-1:4] <= {dw-4{1'b0}};
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wb_dat[dw-1:4] <= {dw-4{1'b0}};
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end
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end
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`endif
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`endif
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default: begin
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default: begin
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wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_in};
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wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_in};
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end
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end
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endcase
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endcase
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//
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//
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// WB data output
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//
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`ifdef GPIO_REGISTERED_WB_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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wb_dat_o <= #1 {dw{1'b0}};
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else
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wb_dat_o <= #1 wb_dat;
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`else
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assign wb_dat_o = wb_dat;
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`endif
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//
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// Generate interrupt request
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// Generate interrupt request
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//
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//
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assign wb_inta_o = ((in_pad_i ^ ~rgpio_ptrig) & rgpio_inte) ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
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assign wb_inta = ((in_pad_i ^ ~rgpio_ptrig) & rgpio_inte) ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
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//
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// Optional registration of WB interrupt
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//
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`ifdef GPIO_REGISTERED_WB_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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wb_inta_o <= #1 wb_inta;
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else
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wb_inta_o <= #1 wb_inta;
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`else
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assign wb_inta_o = wb_inta;
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`endif
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//
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// Output enables are RGPIO_OE bits
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//
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assign oen_padoen_o = rgpio_oe;
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//
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//
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// Generate output enables from inverted RGPIO_OE bits
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// Generate GPIO outputs
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//
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//
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assign oen_padoen_o = ~rgpio_oe;
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assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
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//
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//
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// Generate outputs
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// Optional registration of GPIO outputs
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//
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//
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assign out_pad_o = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
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`ifdef GPIO_REGISTERED_IO_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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out_pad_o <= #1 {gw{1'b0}};
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else
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out_pad_o <= #1 out_pad;
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`else
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assign out_pad_o = out_pad;
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`endif
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`else
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`else
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//
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//
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// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
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// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
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