URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

[/] [gpio/] [tags/] [rel_9/] [rtl/] [verilog/] [gpio_top.v] - Diff between revs 17 and 19

Rev 17	Rev 19
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2001/11/15 02:24:37 lampret`
	`// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.`
	`//`
`// Revision 1.2 2001/10/31 02:26:51 lampret`	`// Revision 1.2 2001/10/31 02:26:51 lampret`
`// Fixed wb_err_o.`	`// Fixed wb_err_o.`
`//`	`//`
`// Revision 1.1 2001/09/18 18:49:07 lampret`	`// Revision 1.1 2001/09/18 18:49:07 lampret`
`// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.`	`// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.`
Line 478...	Line 481...
`// Optional registration of WB interrupt`	`// Optional registration of WB interrupt`
`//`	`//`
`ifdef GPIO_REGISTERED_WB_OUTPUTS	`ifdef GPIO_REGISTERED_WB_OUTPUTS
`always @(posedge wb_clk_i or posedge wb_rst_i)`	`always @(posedge wb_clk_i or posedge wb_rst_i)`
`if (wb_rst_i)`	`if (wb_rst_i)`
`wb_inta_o <= #1 wb_inta;`	`wb_inta_o <= #1 1'b0;`
`else`	`else`
`wb_inta_o <= #1 wb_inta;`	`wb_inta_o <= #1 wb_inta;`
`else	`else
`assign wb_inta_o = wb_inta;`	`assign wb_inta_o = wb_inta;`
`endif	`endif