URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

[/] [gpio/] [trunk/] [bench/] [verilog/] [gpio_testbench.v] - Diff between revs 56 and 63

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Rev 56	Rev 63
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2003/12/17 13:00:14 gorand`
	`// added ECLK and NEC registers, all tests passed.`
	`//`
`// Revision 1.1 2003/11/30 12:28:19 gorand`	`// Revision 1.1 2003/11/30 12:28:19 gorand`
`// small "names" modification...`	`// small "names" modification...`
`//`	`//`
`// Revision 1.5 2003/11/29 16:22:05 gorand`	`// Revision 1.5 2003/11/29 16:22:05 gorand`
`// small changes, for VATS...`	`// small changes, for VATS...`
Line 99...	Line 102...
`wire [gw-1:0] gpio_out; // GPIO outputs`	`wire [gw-1:0] gpio_out; // GPIO outputs`
`wire [gw-1:0] gpio_oen; // GPIO output enables`	`wire [gw-1:0] gpio_oen; // GPIO output enables`
`wire [ 3 : 0 ] tag_o ;`	`wire [ 3 : 0 ] tag_o ;`

`//`	`//`
	`// description of current test.`
	`//`
	`reg [127:0] text;`

	`//`
`// Instantiation of Clock/Reset Generator`	`// Instantiation of Clock/Reset Generator`
`//`	`//`
`clkrst clkrst(`	`clkrst clkrst(`
`// Clock`	`// Clock`
`.clk_o(clk),`	`.clk_o(clk),`
Line 148...	Line 156...
`.wb_ack_o(ack),`	`.wb_ack_o(ack),`
`.wb_err_o(err),`	`.wb_err_o(err),`
`.wb_inta_o(),`	`.wb_inta_o(),`

`// Auxiliary inputs interface`	`// Auxiliary inputs interface`
	`ifdef GPIO_AUX_IMPLEMENT
`.aux_i(gpio_aux),`	`.aux_i(gpio_aux),`
	`endif // GPIO_AUX_IMPLEMENT

`// External GPIO Interface`	`// External GPIO Interface`
`.ext_pad_i(gpio_in),`	`.ext_pad_i(gpio_in),`

	`ifdef GPIO_CLKPAD
`.clk_pad_i(gpio_eclk),`	`.clk_pad_i(gpio_eclk),`
	`endif // GPIO_CLKPAD
`.ext_pad_o(gpio_out),`	`.ext_pad_o(gpio_out),`
`.ext_padoen_o(gpio_oen)`	`.ext_padoe_o(gpio_oen)`
`);`	`);`

`//`	`//`
`// GPIO Monitor`	`// GPIO Monitor`
`//`	`//`
Line 168...	Line 181...
`.gpio_eclk(gpio_eclk),`	`.gpio_eclk(gpio_eclk),`
`.gpio_out(gpio_out),`	`.gpio_out(gpio_out),`
`.gpio_oen(gpio_oen)`	`.gpio_oen(gpio_oen)`
`);`	`);`

	`initial`
	`text = " ";`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [gpio/] [trunk/] [bench/] [verilog/] [gpio_testbench.v] - Diff between revs 56 and 63