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[/] [gpio/] [trunk/] [bench/] [verilog/] [tb_tasks.v] - Diff between revs 18 and 21

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Rev 18 Rev 21
Line 42... Line 42... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.4  2001/11/15 02:26:32  lampret
 
 
 
// Updated timing and fixed some typing errors.
 
 
 
//
 
// Revision 1.3  2001/09/18 16:37:55  lampret
 
// Revision 1.3  2001/09/18 16:37:55  lampret
 
// Changed VCD output location.
 
// Changed VCD output location.
 
//
 
//
 
// Revision 1.2  2001/09/18 15:43:27  lampret
 
// Revision 1.2  2001/09/18 15:43:27  lampret
 
// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.
 
// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.
Line 155... Line 158... 
end
 
end
 
 
 
 
 
endtask
 
endtask
 
 
 
 
 
//
 
//
 
 
 
// Set RGPIO_INTS register
 
 
 
//
 
 
 
task setints;
 
 
 
input   [31:0] val;
 
 
 
 
 
 
 
begin
 
 
 
        #100 tb_top.wb_master.wr(`GPIO_RGPIO_INTS<<sh_addr, val, 4'b1111);
 
 
 
end
 
 
 
 
 
 
 
endtask
 
 
 
 
 
 
 
//
 
// Display RGPIO_IN register
 
// Display RGPIO_IN register
 
//
 
//
 
task showin;
 
task showin;
 
 
 
 
 
reg     [31:0] tmp;
 
reg     [31:0] tmp;
Line 247... Line 262... 
end
 
end
 
 
 
 
 
endtask
 
endtask
 
 
 
 
 
//
 
//
 
 
 
// Display RGPIO_INTS register
 
 
 
//
 
 
 
task showints;
 
 
 
 
 
 
 
reg     [31:0] tmp;
 
 
 
begin
 
 
 
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp);
 
 
 
        $write(" RGPIO_INTS:%h", tmp);
 
 
 
end
 
 
 
 
 
 
 
endtask
 
 
 
 
 
 
 
//
 
// Compare parameter with RGPIO_IN register
 
// Compare parameter with RGPIO_IN register
 
//
 
//
 
task comp_in;
 
task comp_in;
 
input   [31:0]   val;
 
input   [31:0]   val;
 
output          ret;
 
output          ret;
Line 351... Line 379... 
end
 
end
 
 
 
 
 
endtask
 
endtask
 
 
 
 
 
//
 
//
 
 
 
// Get RGPIO_INTS register
 
 
 
//
 
 
 
task getints;
 
 
 
output  [31:0]   tmp;
 
 
 
 
 
 
 
begin
 
 
 
        #100 tb_top.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp);
 
 
 
end
 
 
 
 
 
 
 
endtask
 
 
 
 
 
 
 
//
 
// Calculate a random and make it narrow to fit on GPIO I/O pins
 
// Calculate a random and make it narrow to fit on GPIO I/O pins
 
//
 
//
 
task random_gpio;
 
task random_gpio;
 
output  [31:0]   tmp;
 
output  [31:0]   tmp;
 
 
 
 
Line 688... Line 728... 
 
 
 
 
//
 
//
 
// Test interrupts
 
// Test interrupts
 
//
 
//
 
task test_ints;
 
task test_ints;
 
integer         l1, l2, l3;
 
integer         l1, l2, l3, l4;
 
integer         i, rnd, err;
 
integer         i, rnd, err;
 
integer         r1;
 
integer         r1;
 
begin
 
begin
 
 
 
 
 
        $write("  Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");
 
        $write("  Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");
Line 714... Line 754... 
                tb_top.gpio_mon.set_gpioin(r1);
 
                tb_top.gpio_mon.set_gpioin(r1);
 
 
 
 
 
                // Low level triggering
 
                // Low level triggering
 
                setptrig(0);
 
                setptrig(0);
 
 
 
 
 
 
 
                // Clear RGPIO_INTS
 
 
 
                setints(0);
 
 
 
 
 
                // Enable interrupts in RGPIO_CTRL
 
                // Enable interrupts in RGPIO_CTRL
 
                setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
 
                setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
 
 
 
 
 
                // Enable interrupts in RGPIO_INTE
 
                // Enable interrupts in RGPIO_INTE
 
                setinte(r1);
 
                setinte(r1);
Line 733... Line 776... 
                tb_top.gpio_mon.set_gpioin(0);
 
                tb_top.gpio_mon.set_gpioin(0);
 
 
 
 
 
                // Advance time
 
                // Advance time
 
                @(posedge tb_top.clk);
 
                @(posedge tb_top.clk);
 
                @(posedge tb_top.clk);
 
                @(posedge tb_top.clk);
 
 
 
                @(posedge tb_top.clk);
 
 
 
 
 
                // Sample interrupt request. Should be one.
 
                // Sample interrupt request. Should be one.
 
                l2 = tb_top.gpio_top.wb_inta_o;
 
                l2 = tb_top.gpio_top.wb_inta_o;
 
 
 
 
 
                // Clear interrupt request
 
                // Clear interrupt request
Line 747... Line 791... 
                @(posedge tb_top.clk);
 
                @(posedge tb_top.clk);
 
 
 
 
 
                // Sample interrupt request. Should be zero.
 
                // Sample interrupt request. Should be zero.
 
                l3 = tb_top.gpio_top.wb_inta_o;
 
                l3 = tb_top.gpio_top.wb_inta_o;
 
 
 
 
 
 
 
                // Get RGPIO_INTS. Should be nonzero.
 
 
 
                getints(l4);
 
 
 
 
 
                // Check for errors
 
                // Check for errors
 
                if (l1 || !l2 || l3)
 
                if (l1 || !l2 || l3 || (l4 != r1)) begin
 
 
 
                        $display("l1 %h  l2 %h  l3 %h  l4 %h", l1, l2, l3, l4);
 
                        err = err +1;
 
                        err = err +1;
 
        end
 
        end
 
 
 
        end
 
 
 
 
 
        // Enable spurious interrupt monitor
 
        // Enable spurious interrupt monitor
 
        ints_disabled = 1;
 
        ints_disabled = 1;
 
 
 
 
 
        // Phase 2
 
        // Phase 2
Line 794... Line 843... 
                r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
 
                r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
 
 
 
 
 
                // Set gpio_in pins
 
                // Set gpio_in pins
 
                tb_top.gpio_mon.set_gpioin('h00000000);
 
                tb_top.gpio_mon.set_gpioin('h00000000);
 
 
 
 
 
 
 
                // Clear old interrupts
 
 
 
                setints(0);
 
 
 
 
 
                // High level triggering
 
                // High level triggering
 
                setptrig('hffffffff);
 
                setptrig('hffffffff);
 
 
 
 
 
                // Enable interrupts in RGPIO_CTRL
 
                // Enable interrupts in RGPIO_CTRL
 
                setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
 
                setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
Line 816... Line 868... 
                tb_top.gpio_mon.set_gpioin('hffffffff);
 
                tb_top.gpio_mon.set_gpioin('hffffffff);
 
 
 
 
 
                // Advance time
 
                // Advance time
 
                @(posedge tb_top.clk);
 
                @(posedge tb_top.clk);
 
                @(posedge tb_top.clk);
 
                @(posedge tb_top.clk);
 
 
 
                @(posedge tb_top.clk);
 
 
 
 
 
                // Sample interrupt request. Should be one.
 
                // Sample interrupt request. Should be one.
 
                l2 = tb_top.gpio_top.wb_inta_o;
 
                l2 = tb_top.gpio_top.wb_inta_o;
 
 
 
 
 
                // Clear interrupt request
 
                // Clear interrupt request
 
                setctrl(0);
 
                setctrl(0);
 
 
 
                setints(0);
 
 
 
 
 
                // Advance time
 
                // Advance time
 
                @(posedge tb_top.clk);
 
                @(posedge tb_top.clk);
 
                @(posedge tb_top.clk);
 
                @(posedge tb_top.clk);
 
 
 
 
Line 865... Line 919... 
//
 
//
 
// Start of testbench test tasks
 
// Start of testbench test tasks
 
//
 
//
 
integer         i;
 
integer         i;
 
initial begin
 
initial begin
 
`ifdef DUMP_VCD
 
`ifdef GPIO_DUMP_VCD
 
        $dumpfile("../out/tb_top.vcd");
 
        $dumpfile("../out/tb_top.vcd");
 
        $dumpvars(0);
 
        $dumpvars(0);
 
`endif
 
`endif
 
        nr_failed = 0;
 
        nr_failed = 0;
 
        ints_disabled = 1;
 
        ints_disabled = 1;

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