URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

[/] [gpio/] [trunk/] [bench/] [verilog/] [tb_tasks.v] - Diff between revs 22 and 37

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Rev 22	Rev 37
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.6 2001/12/25 17:21:06 lampret`
	`// Fixed two typos.`
	`//`
`// Revision 1.5 2001/12/25 17:12:28 lampret`	`// Revision 1.5 2001/12/25 17:12:28 lampret`
`// Added RGPIO_INTS.`	`// Added RGPIO_INTS.`
`//`	`//`
`// Revision 1.4 2001/11/15 02:26:32 lampret`	`// Revision 1.4 2001/11/15 02:26:32 lampret`
`// Updated timing and fixed some typing errors.`	`// Updated timing and fixed some typing errors.`
Line 77...	Line 80...
`integer ints_disabled;`	`integer ints_disabled;`
`integer ints_working;`	`integer ints_working;`
`integer local_errs;`	`integer local_errs;`

parameter sh_addr = `GPIO_ADDRLH+1;	parameter sh_addr = `GPIO_ADDRLH+1;
	parameter gw = `GPIO_IOS ;
`//`	`//`
`// Count/report failed tests`	`// Count/report failed tests`
`//`	`//`
`task failed;`	`task failed;`
`begin`	`begin`
Line 94...	Line 97...
`// Set RGPIO_OUT register`	`// Set RGPIO_OUT register`
`//`	`//`
`task setout;`	`task setout;`
`input [31:0] val;`	`input [31:0] val;`

	`reg [ 31:0 ] addr ;`
`begin`	`begin`
	addr = `GPIO_RGPIO_OUT <<sh_addr ;
#100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);	#100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);
	`/* $display ( " addr : %h %h", addr, val ) ;`
	`$display ( " out_pad : %h ", tb_top.gpio_top.out_pad ) ;`
	`$display ( " rgpio_aux : %h ", tb_top.gpio_top.rgpio_aux) ;`
	`$display ( " aux_i : %h ", tb_top.gpio_top.aux_i ) ;`
	`$display ( " rgpio_out : %h ", tb_top.gpio_top.rgpio_out ) ;`
	`*/`
`end`	`end`

`endtask`	`endtask`

`//`	`//`
Line 409...	Line 420...

`//`	`//`
`// Test operation of control bit RGPIO_CTRL[ECLK]`	`// Test operation of control bit RGPIO_CTRL[ECLK]`
`//`	`//`
`task test_eclk;`	`task test_eclk;`
`integer l1, l2, l3;`	`reg [gw-1:0 ] l1, l2, l3;`
`integer r1, r2, r3;`	`reg [gw-1:0 ] r1, r2, r3;`
`begin`	`begin`

`// Set external clock to low state`	`// Set external clock to low state`
`tb_top.gpio_mon.set_gpioeclk(0);`	`tb_top.gpio_mon.set_gpioeclk(0);`
`@(posedge tb_top.clk);`	`@(posedge tb_top.clk);`
Line 568...	Line 579...

`//`	`//`
`// Test input polled mode, output mode and bidirectional`	`// Test input polled mode, output mode and bidirectional`
`//`	`//`
`task test_simple;`	`task test_simple;`
`integer l1, l2, l3, l4;`	`reg [gw-1:0] l1, l2, l3, l4;`
`integer i, err;`	`integer i, err;`
`begin`	`begin`
`$write(" Testing input mode ...");`	`$write(" Testing input mode ...");`

`//`	`//`

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[/] [gpio/] [trunk/] [bench/] [verilog/] [tb_tasks.v] - Diff between revs 22 and 37