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[/] [gpio/] [trunk/] [bench/] [verilog/] [wb_master.v] - Diff between revs 8 and 37
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Rev 37 |
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`include "timescale.v"
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`include "timescale.v"
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`include "gpio_defines.v"
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// -*- Mode: Verilog -*-
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// -*- Mode: Verilog -*-
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// Filename : wb_master.v
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// Filename : wb_master.v
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// Description : Wishbone Master Behavorial
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// Description : Wishbone Master Behavorial
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// Author : Winefred Washington
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// Author : Winefred Washington
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//
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//
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module wb_master(CLK_I, RST_I, TAG_I, TAG_O,
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module wb_master(CLK_I, RST_I, TAG_I, TAG_O,
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ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O);
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ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O);
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parameter aw = `GPIO_ADDRHH+1 ;
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input CLK_I;
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input CLK_I;
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input RST_I;
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input RST_I;
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input [3:0] TAG_I;
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input [3:0] TAG_I;
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output [3:0] TAG_O;
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output [3:0] TAG_O;
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input ACK_I;
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input ACK_I;
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output [31:0] ADR_O;
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output [aw-1:0] ADR_O;
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output CYC_O;
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output CYC_O;
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input [31:0] DAT_I;
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input [31:0] DAT_I;
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output [31:0] DAT_O;
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output [31:0] DAT_O;
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input ERR_I;
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input ERR_I;
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input RTY_I;
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input RTY_I;
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output [3:0] SEL_O;
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output [3:0] SEL_O;
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output STB_O;
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output STB_O;
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output WE_O;
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output WE_O;
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reg [31:0] ADR_O;
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reg [aw-1:0] ADR_O;
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reg [3:0] SEL_O;
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reg [3:0] SEL_O;
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reg CYC_O;
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reg CYC_O;
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reg STB_O;
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reg STB_O;
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reg WE_O;
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reg WE_O;
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reg [31:0] DAT_O;
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reg [31:0] DAT_O;
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