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[/] [gpio/] [trunk/] [rtl/] [verilog/] [gpio_defines.v] - Diff between revs 52 and 56

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.7  2003/12/01 17:10:44  simons
 
// ifndef directive is not supported by all tools.
 
//
// Revision 1.6  2003/11/06 13:59:07  gorand
// Revision 1.6  2003/11/06 13:59:07  gorand
// added support for 8-bit access to registers.
// added support for 8-bit access to registers.
//
//
// Revision 1.2  2003/10/02 18:54:35  simons
// Revision 1.2  2003/10/02 18:54:35  simons
// GPIO signals muxed with other peripherals, higland_board fixed.
// GPIO signals muxed with other peripherals, higland_board fixed.
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//
//
// Default is 16.
// Default is 16.
//
//
`define GPIO_IOS 31
`define GPIO_IOS 31
 
 
 
//depending on number of GPIO_IOS, define this...
 
// for example: if there is 26 GPIO_IOS, define GPIO_LINES26
 
//
 
 
 
`define GPIO_LINES31
 
 
//
//
// Undefine this one if you don't want to remove GPIO block from your design
// Undefine this one if you don't want to remove GPIO block from your design
// but you also don't need it. When it is undefined, all GPIO ports still
// but you also don't need it. When it is undefined, all GPIO ports still
// remain valid and the core can be synthesized however internally there is
// remain valid and the core can be synthesized however internally there is
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//
//
`define GPIO_REGISTERED_IO_OUTPUTS
`define GPIO_REGISTERED_IO_OUTPUTS
 
 
//
//
// Define to avoid using negative edge clock flip-flops for external clock
// Define to avoid using negative edge clock flip-flops for external clock
// (caused by RGPIO_CTRL[NEC] bit. Instead an inverted external clock with
// (caused by NEC register. Instead an inverted external clock with
// positive edge clock flip-flops will be used.
// positive edge clock flip-flops will be used.
//
//
// By default it is not defined.
// By default it is not defined.
//
//
//`define GPIO_NO_NEGEDGE_FLOPS
//`define GPIO_NO_NEGEDGE_FLOPS
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`endif
`endif
 
 
//
//
// WISHBONE address bits used for full decoding of GPIO registers.
// WISHBONE address bits used for full decoding of GPIO registers.
//
//
`define GPIO_ADDRHH 6
`define GPIO_ADDRHH 7
`define GPIO_ADDRHL 5
`define GPIO_ADDRHL 6
`define GPIO_ADDRLH 1
`define GPIO_ADDRLH 1
`define GPIO_ADDRLL 0
`define GPIO_ADDRLL 0
 
 
//
//
// Bits of WISHBONE address used for partial decoding of GPIO registers.
// Bits of WISHBONE address used for partial decoding of GPIO registers.
//
//
// Default 4:2.
// Default 5:2.
//
//
`define GPIO_OFS_BITS   `GPIO_ADDRHL-1:`GPIO_ADDRLH+1
`define GPIO_OFS_BITS   `GPIO_ADDRHL-1:`GPIO_ADDRLH+1
 
 
//
//
// Addresses of GPIO registers
// Addresses of GPIO registers
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//
//
// If particular register is not needed, it's address definition can be omitted
// If particular register is not needed, it's address definition can be omitted
// and the register will not be implemented. Instead a fixed default value will
// and the register will not be implemented. Instead a fixed default value will
// be used.
// be used.
//
//
`define GPIO_RGPIO_IN           3'h0    // Address 0x00
`define GPIO_RGPIO_IN             4'h0  // Address 0x00
`define GPIO_RGPIO_OUT          3'h1    // Address 0x04
`define GPIO_RGPIO_OUT          4'h1    // Address 0x04
`define GPIO_RGPIO_OE           3'h2    // Address 0x08
`define GPIO_RGPIO_OE             4'h2  // Address 0x08
`define GPIO_RGPIO_INTE         3'h3    // Address 0x0c
`define GPIO_RGPIO_INTE         4'h3    // Address 0x0c
`define GPIO_RGPIO_PTRIG        3'h4    // Address 0x10
`define GPIO_RGPIO_PTRIG        4'h4    // Address 0x10
`define GPIO_RGPIO_AUX          3'h5    // Address 0x14
`define GPIO_RGPIO_AUX          4'h5    // Address 0x14
`define GPIO_RGPIO_CTRL         3'h6    // Address 0x18
`define GPIO_RGPIO_CTRL         4'h6    // Address 0x18
`define GPIO_RGPIO_INTS         3'h7    // Address 0x1c
`define GPIO_RGPIO_INTS         4'h7    // Address 0x1c
 
`define GPIO_RGPIO_ECLK   4'h8  // Address 0x20
 
`define GPIO_RGPIO_NEC    4'h9  // Address 0x24
 
 
//
//
// Default values for unimplemented GPIO registers
// Default values for unimplemented GPIO registers
//
//
`define GPIO_DEF_RGPIO_IN       `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_IN       `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_OE       `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_OE       `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_INTE     `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_INTE     `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_PTRIG    `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_PTRIG    `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_AUX      `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_AUX      `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_CTRL     `GPIO_IOS'h0
`define GPIO_DEF_RGPIO_CTRL     `GPIO_IOS'h0
 
`define GPIO_DEF_RGPIO_ECLK `GPIO_IOS'h0
 
`define GPIO_DEF_RGPIO_NEC `GPIO_IOS'h0
 
 
 
 
//
//
// RGPIO_CTRL bits
// RGPIO_CTRL bits
//
//
// To comply with the GPIO IP core specification document they must go from
// To comply with the GPIO IP core specification document they must go from
// bit 0 to bit 3 in the following order: ECLK, NEC, INTE, INT
// bit 0 to bit 1 in the following order: INTE, INT
//
//
`define GPIO_RGPIO_CTRL_ECLK            0
`define GPIO_RGPIO_CTRL_INTE            0
`define GPIO_RGPIO_CTRL_NEC             1
`define GPIO_RGPIO_CTRL_INTS            1
`define GPIO_RGPIO_CTRL_INTE            2
 
`define GPIO_RGPIO_CTRL_INTS            3
`ifdef GPIO_LINES32
 
`define GPIO_LINES31
 
`endif
 
`ifdef GPIO_LINES31
 
`define GPIO_LINES30
 
`endif
 
`ifdef GPIO_LINES30
 
`define GPIO_LINES29
 
`endif
 
`ifdef GPIO_LINES29
 
`define GPIO_LINES28
 
`endif
 
`ifdef GPIO_LINES28
 
`define GPIO_LINES27
 
`endif
 
`ifdef GPIO_LINES27
 
`define GPIO_LINES26
 
`endif
 
`ifdef GPIO_LINES26
 
`define GPIO_LINES25
 
`endif
 
`ifdef GPIO_LINES25
 
`define GPIO_LINES24
 
`endif
 
`ifdef GPIO_LINES24
 
`define GPIO_LINES23
 
`endif
 
`ifdef GPIO_LINES23
 
`define GPIO_LINES22
 
`endif
 
`ifdef GPIO_LINES22
 
`define GPIO_LINES21
 
`endif
 
`ifdef GPIO_LINES21
 
`define GPIO_LINES20
 
`endif
 
`ifdef GPIO_LINES20
 
`define GPIO_LINES19
 
`endif
 
`ifdef GPIO_LINES19
 
`define GPIO_LINES18
 
`endif
 
`ifdef GPIO_LINES18
 
`define GPIO_LINES17
 
`endif
 
`ifdef GPIO_LINES17
 
`define GPIO_LINES16
 
`endif
 
`ifdef GPIO_LINES16
 
`define GPIO_LINES15
 
`endif
 
`ifdef GPIO_LINES15
 
`define GPIO_LINES14
 
`endif
 
`ifdef GPIO_LINES14
 
`define GPIO_LINES13
 
`endif
 
`ifdef GPIO_LINES13
 
`define GPIO_LINES12
 
`endif
 
`ifdef GPIO_LINES12
 
`define GPIO_LINES11
 
`endif
 
`ifdef GPIO_LINES11
 
`define GPIO_LINES10
 
`endif
 
`ifdef GPIO_LINES10
 
`define GPIO_LINES9
 
`endif
 
`ifdef GPIO_LINES9
 
`define GPIO_LINES8
 
`endif
 
`ifdef GPIO_LINES8
 
`define GPIO_LINES7
 
`endif
 
`ifdef GPIO_LINES7
 
`define GPIO_LINES6
 
`endif
 
`ifdef GPIO_LINES6
 
`define GPIO_LINES5
 
`endif
 
`ifdef GPIO_LINES5
 
`define GPIO_LINES4
 
`endif
 
`ifdef GPIO_LINES4
 
`define GPIO_LINES3
 
`endif
 
`ifdef GPIO_LINES3
 
`define GPIO_LINES2
 
`endif
 
`ifdef GPIO_LINES2
 
`define GPIO_LINES1
 
`endif
 
 
 
 
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