| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
|
|
// Revision 1.15 2003/11/10 23:21:22 gorand
|
|
// bug fixed. all tests passed.
|
|
//
|
// Revision 1.14 2003/11/06 13:59:07 gorand
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// Revision 1.14 2003/11/06 13:59:07 gorand
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// added support for 8-bit access to registers.
|
// added support for 8-bit access to registers.
|
//
|
//
|
// Revision 1.13 2002/11/18 22:35:18 lampret
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// Revision 1.13 2002/11/18 22:35:18 lampret
|
// Bug fix. Interrupts were also asserted when condition was not met.
|
// Bug fix. Interrupts were also asserted when condition was not met.
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| Line 203... |
Line 206... |
|
|
//
|
//
|
// GPIO Control Register (or no register)
|
// GPIO Control Register (or no register)
|
//
|
//
|
`ifdef GPIO_RGPIO_CTRL
|
`ifdef GPIO_RGPIO_CTRL
|
reg [3:0] rgpio_ctrl; // RGPIO_CTRL register
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reg [1:0] rgpio_ctrl; // RGPIO_CTRL register
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`else
|
`else
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wire [3:0] rgpio_ctrl; // No register
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wire [1:0] rgpio_ctrl; // No register
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`endif
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`endif
|
|
|
//
|
//
|
// GPIO Interrupt Status Register (or no register)
|
// GPIO Interrupt Status Register (or no register)
|
//
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//
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| Line 218... |
Line 221... |
`else
|
`else
|
wire [gw-1:0] rgpio_ints; // No register
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wire [gw-1:0] rgpio_ints; // No register
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`endif
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`endif
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|
|
//
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//
|
|
// GPIO Enable Clock Register (or no register)
|
|
//
|
|
`ifdef GPIO_RGPIO_ECLK
|
|
reg [gw-1:0] rgpio_eclk; // RGPIO_ECLK register
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`else
|
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wire [gw-1:0] rgpio_eclk; // No register
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|
`endif
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|
|
|
//
|
|
// GPIO Active Negative Edge Register (or no register)
|
|
//
|
|
`ifdef GPIO_RGPIO_NEC
|
|
reg [gw-1:0] rgpio_nec; // RGPIO_NEC register
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|
`else
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|
wire [gw-1:0] rgpio_nec; // No register
|
|
`endif
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|
|
|
//
|
// Internal wires & regs
|
// Internal wires & regs
|
//
|
//
|
wire rgpio_out_sel; // RGPIO_OUT select
|
wire rgpio_out_sel; // RGPIO_OUT select
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wire rgpio_oe_sel; // RGPIO_OE select
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wire rgpio_oe_sel; // RGPIO_OE select
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wire rgpio_inte_sel; // RGPIO_INTE select
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wire rgpio_inte_sel; // RGPIO_INTE select
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wire rgpio_ptrig_sel;// RGPIO_PTRIG select
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wire rgpio_ptrig_sel;// RGPIO_PTRIG select
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wire rgpio_aux_sel; // RGPIO_AUX select
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wire rgpio_aux_sel; // RGPIO_AUX select
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wire rgpio_ctrl_sel; // RGPIO_CTRL select
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wire rgpio_ctrl_sel; // RGPIO_CTRL select
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wire rgpio_ints_sel; // RGPIO_INTS select
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wire rgpio_ints_sel; // RGPIO_INTS select
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wire latch_clk; // Latch clock
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wire rgpio_eclk_sel ;
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|
wire rgpio_nec_sel ;
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wire full_decoding; // Full address decoding qualification
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wire full_decoding; // Full address decoding qualification
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wire [gw-1:0] in_muxed; // Muxed inputs
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wire [gw-1:0] in_muxed; // Muxed inputs
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wire wb_ack; // WB Acknowledge
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wire wb_ack; // WB Acknowledge
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wire wb_err; // WB Error
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wire wb_err; // WB Error
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wire wb_inta; // WB Interrupt
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wire wb_inta; // WB Interrupt
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| Line 245... |
Line 267... |
wire [gw-1:0] out_pad; // GPIO Outputs
|
wire [gw-1:0] out_pad; // GPIO Outputs
|
`ifdef GPIO_REGISTERED_IO_OUTPUTS
|
`ifdef GPIO_REGISTERED_IO_OUTPUTS
|
reg [gw-1:0] ext_pad_o; // GPIO Outputs
|
reg [gw-1:0] ext_pad_o; // GPIO Outputs
|
`endif
|
`endif
|
wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock
|
wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock
|
wire pext_clk; // External clock for posedge flops
|
wire [gw-1:0] pext_clk; // External clock for posedge flops
|
reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs
|
reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
`else
|
`else
|
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
|
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
|
`endif
|
`endif
|
|
|
|
|
//
|
//
|
// All WISHBONE transfer terminations are successful except when:
|
// All WISHBONE transfer terminations are successful except when:
|
// a) full address decoding is enabled and address doesn't match
|
// a) full address decoding is enabled and address doesn't match
|
// any of the GPIO registers
|
// any of the GPIO registers
|
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
|
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
|
| Line 328... |
Line 351... |
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
|
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
|
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
|
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
|
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
|
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
|
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
|
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
|
|
|
|
assign rgpio_eclk_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding;
|
|
assign rgpio_nec_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding;
|
|
|
|
|
|
|
//
|
//
|
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
|
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
|
//
|
//
|
`ifdef GPIO_RGPIO_CTRL
|
`ifdef GPIO_RGPIO_CTRL
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
rgpio_ctrl <= #1 4'b0;
|
rgpio_ctrl <= #1 2'b0;
|
else if (rgpio_ctrl_sel && wb_we_i)
|
else if (rgpio_ctrl_sel && wb_we_i)
|
rgpio_ctrl <= #1 wb_dat_i[3:0];
|
rgpio_ctrl <= #1 wb_dat_i[1:0];
|
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
|
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
|
rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
|
rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
|
`else
|
`else
|
assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1
|
assign rgpio_ctrl = 2'h01; // RGPIO_CTRL[EN] = 1
|
`endif
|
`endif
|
|
|
//
|
//
|
// Write to RGPIO_OUT
|
// Write to RGPIO_OUT
|
//
|
//
|
| Line 579... |
Line 607... |
|
|
`else
|
`else
|
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
|
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
|
`endif
|
`endif
|
|
|
|
|
|
//
|
|
// Write to RGPIO_ECLK
|
|
//
|
|
`ifdef GPIO_RGPIO_ECLK
|
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
rgpio_eclk <= #1 {gw{1'b0}};
|
|
else if (rgpio_eclk_sel && wb_we_i)
|
|
begin
|
|
`ifdef GPIO_STRICT_32BIT_ACCESS
|
|
rgpio_eclk <= #1 wb_dat_i[gw-1:0];
|
|
`endif
|
|
|
|
`ifdef GPIO_WB_BYTES4
|
|
if ( wb_sel_i [3] == 1'b1 )
|
|
rgpio_eclk [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
|
|
if ( wb_sel_i [2] == 1'b1 )
|
|
rgpio_eclk [23:16] <= #1 wb_dat_i [23:16] ;
|
|
if ( wb_sel_i [1] == 1'b1 )
|
|
rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ;
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
|
|
`endif
|
|
`ifdef GPIO_WB_BYTES3
|
|
if ( wb_sel_i [2] == 1'b1 )
|
|
rgpio_eclk [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
|
|
if ( wb_sel_i [1] == 1'b1 )
|
|
rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ;
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
|
|
`endif
|
|
`ifdef GPIO_WB_BYTES2
|
|
if ( wb_sel_i [1] == 1'b1 )
|
|
rgpio_eclk [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
|
|
`endif
|
|
`ifdef GPIO_WB_BYTES1
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_eclk [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
|
|
`endif
|
|
end
|
|
|
|
|
|
`else
|
|
assign rgpio_eclk = `GPIO_DEF_RPGIO_ECLK; // RGPIO_ECLK = 0x0
|
|
`endif
|
|
|
|
|
|
|
|
//
|
|
// Write to RGPIO_NEC
|
|
//
|
|
`ifdef GPIO_RGPIO_NEC
|
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
rgpio_nec <= #1 {gw{1'b0}};
|
|
else if (rgpio_nec_sel && wb_we_i)
|
|
begin
|
|
`ifdef GPIO_STRICT_32BIT_ACCESS
|
|
rgpio_nec <= #1 wb_dat_i[gw-1:0];
|
|
`endif
|
|
|
|
`ifdef GPIO_WB_BYTES4
|
|
if ( wb_sel_i [3] == 1'b1 )
|
|
rgpio_nec [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
|
|
if ( wb_sel_i [2] == 1'b1 )
|
|
rgpio_nec [23:16] <= #1 wb_dat_i [23:16] ;
|
|
if ( wb_sel_i [1] == 1'b1 )
|
|
rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ;
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
|
|
`endif
|
|
`ifdef GPIO_WB_BYTES3
|
|
if ( wb_sel_i [2] == 1'b1 )
|
|
rgpio_nec [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
|
|
if ( wb_sel_i [1] == 1'b1 )
|
|
rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ;
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
|
|
`endif
|
|
`ifdef GPIO_WB_BYTES2
|
|
if ( wb_sel_i [1] == 1'b1 )
|
|
rgpio_nec [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
|
|
`endif
|
|
`ifdef GPIO_WB_BYTES1
|
|
if ( wb_sel_i [0] == 1'b1 )
|
|
rgpio_nec [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
|
|
`endif
|
|
end
|
|
|
|
|
|
`else
|
|
assign rgpio_nec = `GPIO_DEF_RPGIO_NEC; // RGPIO_NEC = 0x0
|
|
`endif
|
|
|
|
|
//
|
//
|
// Latch into RGPIO_IN
|
// Latch into RGPIO_IN
|
//
|
//
|
`ifdef GPIO_RGPIO_IN
|
`ifdef GPIO_RGPIO_IN
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
| Line 595... |
Line 723... |
`endif
|
`endif
|
|
|
//
|
//
|
// Mux inputs directly from input pads with inputs sampled by external clock
|
// Mux inputs directly from input pads with inputs sampled by external clock
|
//
|
//
|
assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
|
//assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;
|
|
|
|
|
|
`ifdef GPIO_LINES32
|
|
assign in_muxed [31] = rgpio_eclk [31] ? extc_in[31] : ext_pad_i[31] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES31
|
|
assign in_muxed [30] = rgpio_eclk [30] ? extc_in[30] : ext_pad_i[30] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES30
|
|
assign in_muxed [29] = rgpio_eclk [29] ? extc_in[29] : ext_pad_i[29] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES29
|
|
assign in_muxed [28] = rgpio_eclk [28] ? extc_in[28] : ext_pad_i[28] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES28
|
|
assign in_muxed [27] = rgpio_eclk [27] ? extc_in[27] : ext_pad_i[27] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES27
|
|
assign in_muxed [26] = rgpio_eclk [26] ? extc_in[26] : ext_pad_i[26] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES26
|
|
assign in_muxed [25] = rgpio_eclk [25] ? extc_in[25] : ext_pad_i[25] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES25
|
|
assign in_muxed [24] = rgpio_eclk [24] ? extc_in[24] : ext_pad_i[24] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES24
|
|
assign in_muxed [23] = rgpio_eclk [23] ? extc_in[23] : ext_pad_i[23] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES23
|
|
assign in_muxed [22] = rgpio_eclk [22] ? extc_in[22] : ext_pad_i[22] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES22
|
|
assign in_muxed [21] = rgpio_eclk [21] ? extc_in[21] : ext_pad_i[21] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES21
|
|
assign in_muxed [20] = rgpio_eclk [20] ? extc_in[20] : ext_pad_i[20] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES20
|
|
assign in_muxed [19] = rgpio_eclk [19] ? extc_in[19] : ext_pad_i[19] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES19
|
|
assign in_muxed [18] = rgpio_eclk [18] ? extc_in[18] : ext_pad_i[18] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES18
|
|
assign in_muxed [17] = rgpio_eclk [17] ? extc_in[17] : ext_pad_i[17] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES17
|
|
assign in_muxed [16] = rgpio_eclk [16] ? extc_in[16] : ext_pad_i[16] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES16
|
|
assign in_muxed [15] = rgpio_eclk [15] ? extc_in[15] : ext_pad_i[15] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES15
|
|
assign in_muxed [14] = rgpio_eclk [14] ? extc_in[14] : ext_pad_i[14] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES14
|
|
assign in_muxed [13] = rgpio_eclk [13] ? extc_in[13] : ext_pad_i[13] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES13
|
|
assign in_muxed [12] = rgpio_eclk [12] ? extc_in[12] : ext_pad_i[12] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES12
|
|
assign in_muxed [11] = rgpio_eclk [11] ? extc_in[11] : ext_pad_i[11] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES11
|
|
assign in_muxed [10] = rgpio_eclk [10] ? extc_in[10] : ext_pad_i[10] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES10
|
|
assign in_muxed [9] = rgpio_eclk [9] ? extc_in[9] : ext_pad_i[9] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES9
|
|
assign in_muxed [8] = rgpio_eclk [8] ? extc_in[8] : ext_pad_i[8] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES8
|
|
assign in_muxed [7] = rgpio_eclk [7] ? extc_in[7] : ext_pad_i[7] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES7
|
|
assign in_muxed [6] = rgpio_eclk [6] ? extc_in[6] : ext_pad_i[6] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES6
|
|
assign in_muxed [5] = rgpio_eclk [5] ? extc_in[5] : ext_pad_i[5] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES5
|
|
assign in_muxed [4] = rgpio_eclk [4] ? extc_in[4] : ext_pad_i[4] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES4
|
|
assign in_muxed [3] = rgpio_eclk [3] ? extc_in[3] : ext_pad_i[3] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES3
|
|
assign in_muxed [2] = rgpio_eclk [2] ? extc_in[2] : ext_pad_i[2] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES2
|
|
assign in_muxed [1] = rgpio_eclk [1] ? extc_in[1] : ext_pad_i[1] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES1
|
|
assign in_muxed [0] = rgpio_eclk [0] ? extc_in[0] : ext_pad_i[0] ;
|
|
`endif
|
|
|
|
|
//
|
//
|
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
|
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
|
// If negedge flops are allowed, pext_clk only clocks posedge flops.
|
// If negedge flops are allowed, pext_clk only clocks posedge flops.
|
//
|
//
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
`ifdef GPIO_NO_CLKPAD_LOGIC
|
`ifdef GPIO_NO_CLKPAD_LOGIC
|
assign pext_clk = clk_pad_i;
|
assign pext_clk = {gw{clk_pad_i}};
|
`else
|
`else
|
assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
|
|
|
//assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;
|
|
|
|
|
|
`ifdef GPIO_LINES32
|
|
assign pext_clk [31] = rgpio_nec [31] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES31
|
|
assign pext_clk [30] = rgpio_nec [30] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES30
|
|
assign pext_clk [29] = rgpio_nec [29] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES29
|
|
assign pext_clk [28] = rgpio_nec [28] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES28
|
|
assign pext_clk [27] = rgpio_nec [27] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES27
|
|
assign pext_clk [26] = rgpio_nec [26] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES26
|
|
assign pext_clk [25] = rgpio_nec [25] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES25
|
|
assign pext_clk [24] = rgpio_nec [24] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES24
|
|
assign pext_clk [23] = rgpio_nec [23] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES23
|
|
assign pext_clk [22] = rgpio_nec [22] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES22
|
|
assign pext_clk [21] = rgpio_nec [21] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES21
|
|
assign pext_clk [20] = rgpio_nec [20] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES20
|
|
assign pext_clk [19] = rgpio_nec [19] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES19
|
|
assign pext_clk [18] = rgpio_nec [18] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES18
|
|
assign pext_clk [17] = rgpio_nec [17] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES17
|
|
assign pext_clk [16] = rgpio_nec [16] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES16
|
|
assign pext_clk [15] = rgpio_nec [15] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES15
|
|
assign pext_clk [14] = rgpio_nec [14] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES14
|
|
assign pext_clk [13] = rgpio_nec [13] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES13
|
|
assign pext_clk [12] = rgpio_nec [12] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES12
|
|
assign pext_clk [11] = rgpio_nec [11] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES11
|
|
assign pext_clk [10] = rgpio_nec [10] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES10
|
|
assign pext_clk [9] = rgpio_nec [9] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES9
|
|
assign pext_clk [8] = rgpio_nec [8] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES8
|
|
assign pext_clk [7] = rgpio_nec [7] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES7
|
|
assign pext_clk [6] = rgpio_nec [6] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES6
|
|
assign pext_clk [5] = rgpio_nec [5] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES5
|
|
assign pext_clk [4] = rgpio_nec [4] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES4
|
|
assign pext_clk [3] = rgpio_nec [3] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES3
|
|
assign pext_clk [2] = rgpio_nec [2] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES2
|
|
assign pext_clk [1] = rgpio_nec [1] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES1
|
|
assign pext_clk [0] = rgpio_nec [0] ? ~clk_pad_i : clk_pad_i ;
|
|
`endif
|
|
|
`endif
|
`endif
|
`else
|
`else
|
assign pext_clk = clk_pad_i;
|
assign pext_clk = {gw{clk_pad_i}};
|
`endif
|
`endif
|
|
|
|
|
//
|
//
|
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
|
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
|
//
|
//
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
assign extc_in = pextc_sampled;
|
assign extc_in = pextc_sampled;
|
`else
|
`else
|
assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
|
//assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
|
|
|
|
|
|
`ifdef GPIO_LINES32
|
|
assign extc_in [31] = rgpio_nec [31] ? nextc_sampled[31] : pextc_sampled[31] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES31
|
|
assign extc_in [30] = rgpio_nec [30] ? nextc_sampled[30] : pextc_sampled[30] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES30
|
|
assign extc_in [29] = rgpio_nec [29] ? nextc_sampled[29] : pextc_sampled[29] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES29
|
|
assign extc_in [28] = rgpio_nec [28] ? nextc_sampled[28] : pextc_sampled[28] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES28
|
|
assign extc_in [27] = rgpio_nec [27] ? nextc_sampled[27] : pextc_sampled[27] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES27
|
|
assign extc_in [26] = rgpio_nec [26] ? nextc_sampled[26] : pextc_sampled[26] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES26
|
|
assign extc_in [25] = rgpio_nec [25] ? nextc_sampled[25] : pextc_sampled[25] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES25
|
|
assign extc_in [24] = rgpio_nec [24] ? nextc_sampled[24] : pextc_sampled[24] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES24
|
|
assign extc_in [23] = rgpio_nec [23] ? nextc_sampled[23] : pextc_sampled[23] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES23
|
|
assign extc_in [22] = rgpio_nec [22] ? nextc_sampled[22] : pextc_sampled[22] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES22
|
|
assign extc_in [21] = rgpio_nec [21] ? nextc_sampled[21] : pextc_sampled[21] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES21
|
|
assign extc_in [20] = rgpio_nec [20] ? nextc_sampled[20] : pextc_sampled[20] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES20
|
|
assign extc_in [19] = rgpio_nec [19] ? nextc_sampled[19] : pextc_sampled[19] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES19
|
|
assign extc_in [18] = rgpio_nec [18] ? nextc_sampled[18] : pextc_sampled[18] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES18
|
|
assign extc_in [17] = rgpio_nec [17] ? nextc_sampled[17] : pextc_sampled[17] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES17
|
|
assign extc_in [16] = rgpio_nec [16] ? nextc_sampled[16] : pextc_sampled[16] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES16
|
|
assign extc_in [15] = rgpio_nec [15] ? nextc_sampled[15] : pextc_sampled[15] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES15
|
|
assign extc_in [14] = rgpio_nec [14] ? nextc_sampled[14] : pextc_sampled[14] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES14
|
|
assign extc_in [13] = rgpio_nec [13] ? nextc_sampled[13] : pextc_sampled[13] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES13
|
|
assign extc_in [12] = rgpio_nec [12] ? nextc_sampled[12] : pextc_sampled[12] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES12
|
|
assign extc_in [11] = rgpio_nec [11] ? nextc_sampled[11] : pextc_sampled[11] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES11
|
|
assign extc_in [10] = rgpio_nec [10] ? nextc_sampled[10] : pextc_sampled[10] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES10
|
|
assign extc_in [9] = rgpio_nec [9] ? nextc_sampled[9] : pextc_sampled[9] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES9
|
|
assign extc_in [8] = rgpio_nec [8] ? nextc_sampled[8] : pextc_sampled[8] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES8
|
|
assign extc_in [7] = rgpio_nec [7] ? nextc_sampled[7] : pextc_sampled[7] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES7
|
|
assign extc_in [6] = rgpio_nec [6] ? nextc_sampled[6] : pextc_sampled[6] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES6
|
|
assign extc_in [5] = rgpio_nec [5] ? nextc_sampled[5] : pextc_sampled[5] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES5
|
|
assign extc_in [4] = rgpio_nec [4] ? nextc_sampled[4] : pextc_sampled[4] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES4
|
|
assign extc_in [3] = rgpio_nec [3] ? nextc_sampled[3] : pextc_sampled[3] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES3
|
|
assign extc_in [2] = rgpio_nec [2] ? nextc_sampled[2] : pextc_sampled[2] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES2
|
|
assign extc_in [1] = rgpio_nec [1] ? nextc_sampled[1] : pextc_sampled[1] ;
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES1
|
|
assign extc_in [0] = rgpio_nec [0] ? nextc_sampled[0] : pextc_sampled[0] ;
|
|
`endif
|
|
|
`endif
|
`endif
|
|
|
//
|
//
|
// Latch using posedge external clock
|
// Latch using posedge external clock
|
//
|
//
|
always @(posedge pext_clk or posedge wb_rst_i)
|
|
|
`ifdef GPIO_LINES32
|
|
always @(posedge pext_clk[31] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[31] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[31] <= #1 ext_pad_i[31];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES31
|
|
always @(posedge pext_clk[30] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[30] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[30] <= #1 ext_pad_i[30];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES30
|
|
always @(posedge pext_clk[29] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[29] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[29] <= #1 ext_pad_i[29];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES29
|
|
always @(posedge pext_clk[28] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[28] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[28] <= #1 ext_pad_i[28];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES28
|
|
always @(posedge pext_clk[27] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[27] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[27] <= #1 ext_pad_i[27];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES27
|
|
always @(posedge pext_clk[26] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[26] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[26] <= #1 ext_pad_i[26];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES26
|
|
always @(posedge pext_clk[25] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[25] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[25] <= #1 ext_pad_i[25];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES25
|
|
always @(posedge pext_clk[24] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[24] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[24] <= #1 ext_pad_i[24];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES24
|
|
always @(posedge pext_clk[23] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[23] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[23] <= #1 ext_pad_i[23];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES23
|
|
always @(posedge pext_clk[22] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[22] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[22] <= #1 ext_pad_i[22];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES22
|
|
always @(posedge pext_clk[21] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[21] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[21] <= #1 ext_pad_i[21];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES21
|
|
always @(posedge pext_clk[20] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[20] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[20] <= #1 ext_pad_i[20];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES20
|
|
always @(posedge pext_clk[19] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[19] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[19] <= #1 ext_pad_i[19];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES19
|
|
always @(posedge pext_clk[18] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[18] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[18] <= #1 ext_pad_i[18];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES18
|
|
always @(posedge pext_clk[17] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[17] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[17] <= #1 ext_pad_i[17];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES17
|
|
always @(posedge pext_clk[16] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[16] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[16] <= #1 ext_pad_i[16];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES16
|
|
always @(posedge pext_clk[15] or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
pextc_sampled <= #1 {gw{1'b0}};
|
pextc_sampled[15] <= #1 1'b0;
|
else
|
else
|
pextc_sampled <= #1 ext_pad_i;
|
pextc_sampled[15] <= #1 ext_pad_i[15];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES15
|
|
always @(posedge pext_clk[14] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[14] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[14] <= #1 ext_pad_i[14];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES14
|
|
always @(posedge pext_clk[13] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[13] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[13] <= #1 ext_pad_i[13];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES13
|
|
always @(posedge pext_clk[12] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[12] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[12] <= #1 ext_pad_i[12];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES12
|
|
always @(posedge pext_clk[11] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[11] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[11] <= #1 ext_pad_i[11];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES11
|
|
always @(posedge pext_clk[10] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[10] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[10] <= #1 ext_pad_i[10];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES10
|
|
always @(posedge pext_clk[9] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[9] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[9] <= #1 ext_pad_i[9];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES9
|
|
always @(posedge pext_clk[8] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[8] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[8] <= #1 ext_pad_i[8];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES8
|
|
always @(posedge pext_clk[7] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[7] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[7] <= #1 ext_pad_i[7];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES7
|
|
always @(posedge pext_clk[6] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[6] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[6] <= #1 ext_pad_i[6];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES6
|
|
always @(posedge pext_clk[5] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[5] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[5] <= #1 ext_pad_i[5];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES5
|
|
always @(posedge pext_clk[4] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[4] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[4] <= #1 ext_pad_i[4];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES4
|
|
always @(posedge pext_clk[3] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[3] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[3] <= #1 ext_pad_i[3];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES3
|
|
always @(posedge pext_clk[2] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[2] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[2] <= #1 ext_pad_i[2];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES2
|
|
always @(posedge pext_clk[1] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[1] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[1] <= #1 ext_pad_i[1];
|
|
`endif
|
|
|
|
`ifdef GPIO_LINES1
|
|
always @(posedge pext_clk[0] or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
pextc_sampled[0] <= #1 1'b0;
|
|
else
|
|
pextc_sampled[0] <= #1 ext_pad_i[0];
|
|
`endif
|
|
|
//
|
//
|
// Latch using negedge external clock
|
// Latch using negedge external clock
|
//
|
//
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
| Line 645... |
Line 1416... |
|
|
//
|
//
|
// Mux all registers when doing a read of GPIO registers
|
// Mux all registers when doing a read of GPIO registers
|
//
|
//
|
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
|
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
|
rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints)
|
rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints or rgpio_eclk or rgpio_nec)
|
case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
|
case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
|
`ifdef GPIO_READREGS
|
`ifdef GPIO_READREGS
|
`GPIO_RGPIO_OUT: begin
|
`GPIO_RGPIO_OUT: begin
|
wb_dat[dw-1:0] = rgpio_out;
|
wb_dat[dw-1:0] = rgpio_out;
|
end
|
end
|
| Line 660... |
Line 1431... |
wb_dat[dw-1:0] = rgpio_inte;
|
wb_dat[dw-1:0] = rgpio_inte;
|
end
|
end
|
`GPIO_RGPIO_PTRIG: begin
|
`GPIO_RGPIO_PTRIG: begin
|
wb_dat[dw-1:0] = rgpio_ptrig;
|
wb_dat[dw-1:0] = rgpio_ptrig;
|
end
|
end
|
|
`GPIO_RGPIO_NEC: begin
|
|
wb_dat[dw-1:0] = rgpio_nec;
|
|
end
|
|
`GPIO_RGPIO_ECLK: begin
|
|
wb_dat[dw-1:0] = rgpio_eclk;
|
|
end
|
`GPIO_RGPIO_AUX: begin
|
`GPIO_RGPIO_AUX: begin
|
wb_dat[dw-1:0] = rgpio_aux;
|
wb_dat[dw-1:0] = rgpio_aux;
|
end
|
end
|
`GPIO_RGPIO_CTRL: begin
|
`GPIO_RGPIO_CTRL: begin
|
wb_dat[3:0] = rgpio_ctrl;
|
wb_dat[1:0] = rgpio_ctrl;
|
wb_dat[dw-1:4] = {dw-4{1'b0}};
|
wb_dat[dw-1:2] = {dw-2{1'b0}};
|
end
|
end
|
`endif
|
`endif
|
`GPIO_RGPIO_INTS: begin
|
`GPIO_RGPIO_INTS: begin
|
wb_dat[dw-1:0] = rgpio_ints;
|
wb_dat[dw-1:0] = rgpio_ints;
|
end
|
end
|
| Line 766... |
Line 1543... |
|
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
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|
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|
|
|
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|
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|
