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[/] [ha1588/] [tags/] [v1p2/] [rtl/] [rtc/] [rtc.v] - Diff between revs 41 and 45
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Rev 41 |
Rev 45 |
Line 102... |
Line 102... |
reg [37:0] time_acc_30n_08f_pre_neg; // 37:8 ns , 7:0 ns_fraction
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reg [37:0] time_acc_30n_08f_pre_neg; // 37:8 ns , 7:0 ns_fraction
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wire time_acc_48s_inc = (time_acc_30n_08f_pre_pos >= time_acc_modulo)? 1'b1: 1'b0;
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wire time_acc_48s_inc = (time_acc_30n_08f_pre_pos >= time_acc_modulo)? 1'b1: 1'b0;
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// time accumulator pre adder (48bit_s + 30bit_ns + 8bit_ns_fraction)
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// time accumulator pre adder (48bit_s + 30bit_ns + 8bit_ns_fraction)
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always @(posedge rst or posedge clk) begin
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always @(posedge rst or posedge clk) begin
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if (rst) begin
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if (rst) begin
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time_acc_30n_08f_pre_pos <= {22'd0, time_adj_08n_08f};
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time_acc_30n_08f_pre_pos <= 38'd0;
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time_acc_30n_08f_pre_neg <= {22'd0, time_adj_08n_08f};
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time_acc_30n_08f_pre_neg <= 38'd0;
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end
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end
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else begin
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else begin
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if (time_ld) begin // direct write
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if (time_ld) begin // direct write
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time_acc_30n_08f_pre_pos <= time_reg_ns_in + {22'd0, time_adj_08n_08f};
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time_acc_30n_08f_pre_pos <= time_reg_ns_in + {22'd0, time_adj_08n_08f};
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time_acc_30n_08f_pre_neg <= time_reg_ns_in + {22'd0, time_adj_08n_08f};
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time_acc_30n_08f_pre_neg <= time_reg_ns_in + {22'd0, time_adj_08n_08f};
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