| Line 6... |
Line 6... |
input gmii_clk,
|
input gmii_clk,
|
input gmii_ctrl,
|
input gmii_ctrl,
|
input [7:0] gmii_data,
|
input [7:0] gmii_data,
|
|
|
input rtc_timer_clk,
|
input rtc_timer_clk,
|
input [79:0] rtc_timer_in,
|
input [29:0] rtc_timer_in,
|
|
|
input q_rst,
|
input q_rst,
|
input q_rd_clk,
|
input q_rd_clk,
|
input q_rd_en,
|
input q_rd_en,
|
output [ 7:0] q_rd_stat,
|
output [ 7:0] q_rd_stat,
|
output [91:0] q_rd_data
|
output [47:0] q_rd_data
|
);
|
);
|
|
|
// buffer gmii input
|
// buffer gmii input
|
reg int_gmii_ctrl;
|
reg int_gmii_ctrl;
|
reg int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4, int_gmii_ctrl_d5;
|
reg int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4, int_gmii_ctrl_d5;
|
| Line 58... |
Line 58... |
ts_req_d1 <= ts_req;
|
ts_req_d1 <= ts_req;
|
ts_req_d2 <= ts_req_d1;
|
ts_req_d2 <= ts_req_d1;
|
ts_req_d3 <= ts_req_d2;
|
ts_req_d3 <= ts_req_d2;
|
end
|
end
|
end
|
end
|
reg [79:0] rtc_time_stamp;
|
reg [29:0] rtc_time_stamp;
|
always @(posedge rst or posedge rtc_timer_clk) begin
|
always @(posedge rst or posedge rtc_timer_clk) begin
|
if (rst)
|
if (rst)
|
rtc_time_stamp <= 80'd0;
|
rtc_time_stamp <= 30'd0;
|
else
|
else
|
if (ts_req_d2 & !ts_req_d3)
|
if (ts_req_d2 & !ts_req_d3)
|
rtc_time_stamp <= rtc_timer_in;
|
rtc_time_stamp <= rtc_timer_in;
|
end
|
end
|
reg ts_ack, ts_ack_clr;
|
reg ts_ack, ts_ack_clr;
|
| Line 88... |
Line 88... |
ts_ack_d1 <= ts_ack;
|
ts_ack_d1 <= ts_ack;
|
ts_ack_d2 <= ts_ack_d1;
|
ts_ack_d2 <= ts_ack_d1;
|
ts_ack_d3 <= ts_ack_d2;
|
ts_ack_d3 <= ts_ack_d2;
|
end
|
end
|
end
|
end
|
reg [79:0] gmii_time_stamp;
|
reg [29:0] gmii_time_stamp;
|
always @(posedge rst or posedge gmii_clk) begin
|
always @(posedge rst or posedge gmii_clk) begin
|
if (rst) begin
|
if (rst) begin
|
gmii_time_stamp <= 80'd0;
|
gmii_time_stamp <= 30'd0;
|
ts_ack_clr <= 1'b0;
|
ts_ack_clr <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
if (ts_ack_d2 & !ts_ack_d3) begin
|
if (ts_ack_d2 & !ts_ack_d3) begin
|
gmii_time_stamp <= rtc_time_stamp;
|
gmii_time_stamp <= rtc_time_stamp;
|
| Line 160... |
Line 160... |
end
|
end
|
|
|
// ptp packet parser here
|
// ptp packet parser here
|
// works at 1/4 gmii_clk frequency, needs multicycle timing constraint
|
// works at 1/4 gmii_clk frequency, needs multicycle timing constraint
|
wire ptp_found;
|
wire ptp_found;
|
wire [91:0] ptp_infor;
|
wire [41:0] ptp_infor;
|
ptp_parser parser(
|
ptp_parser parser(
|
.clk(gmii_clk),
|
.clk(gmii_clk),
|
.rst(rst),
|
.rst(rst),
|
.ptp_data(int_data),
|
.ptp_data(int_data),
|
.ptp_valid(int_valid),
|
.ptp_valid(int_valid),
|
| Line 177... |
Line 177... |
);
|
);
|
|
|
// ptp time stamp dcfifo
|
// ptp time stamp dcfifo
|
wire q_wr_clk = gmii_clk;
|
wire q_wr_clk = gmii_clk;
|
wire q_wr_en = ptp_found;
|
wire q_wr_en = ptp_found;
|
wire [95:0] q_wr_data = {4'd0, ptp_infor};
|
wire [47:0] q_wr_data = {6'd0, ptp_infor};
|
wire [2:0] q_wrusedw;
|
wire [3:0] q_wrusedw;
|
wire [2:0] q_rdusedw;
|
wire [3:0] q_rdusedw;
|
|
|
ptp_queue queue(
|
ptp_queue queue(
|
.aclr(q_rst),
|
.aclr(q_rst),
|
|
|
.wrclk(q_wr_clk),
|
.wrclk(q_wr_clk),
|
.wrreq(q_wr_en && q_wrusedw<=5),
|
.wrreq(q_wr_en && q_wrusedw<=15),
|
.data(q_wr_data),
|
.data(q_wr_data),
|
.wrusedw(q_wrusedw),
|
.wrusedw(q_wrusedw),
|
|
|
.rdclk(q_rd_clk),
|
.rdclk(q_rd_clk),
|
.rdreq(q_rd_en && q_rdusedw>=1),
|
.rdreq(q_rd_en && q_rdusedw>=1),
|
.q(q_rd_data),
|
.q(q_rd_data),
|
.rdusedw(q_rdusedw)
|
.rdusedw(q_rdusedw)
|
);
|
);
|
|
|
assign q_rd_stat = {5'd0, q_rdusedw};
|
assign q_rd_stat = {4'd0, q_rdusedw};
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
