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General Description
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Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packet transmitting and receiving is implemented by PTP SW protocol stack with any existing MAC function internal or external to the FPGA; The IP Core implements the Real-Time Clock (RTC) and Time Stamping of PTP event packets (TSU).
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Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packet transmitting and receiving is implemented with any existing MAC inside or outside the FPAG; The IP Core will implement the tunable Real-Time Clock and Time Stamping of PTP event packets (L2, UDP/IPv4/MPLS/VLAN and UDP/IPv6/MPLS/VLAN) in two-step-mode.
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Feature Description
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Feature Description
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RTC: Real Time Clock.
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RTC: Real Time Clock.
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* Standard PTP clock output with 2^48s and 2^32ns time resolution.
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* Standard PTP clock output with 2^48s and 2^32ns time format.
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* Tunable accumulator based clock with 2^-8ns time resolution and 2^-32ns period resolution.
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* Tunable accumulator based clock with 2^-8ns time resolution and 2^-32ns period resolution.
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** Direct ToD write, with 2^-8ns resolution.
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** Direct time write, with 2^-8ns resolution.
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** Direct frequency write, with 2^-32ns resolution.
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** Direct frequency write, with 2^-32ns resolution.
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** Timed temporary time adjustment, with 2^-8ns resolution and 2^32bit timer.
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** Timed temporary time adjustment, with 2^-8ns resolution and 32bit timer.
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* Clock Domain Crossing hand-shaking, for SW read and write accesses.
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* Variety of input clock frequencies.
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* Clock Domain Crossing hand-shaking, for SW read and write access.
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TSU: Time Stamping Unit.
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TSU: Time Stamping Unit.
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* Two-Step PTP operation.
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* Two-Step PTP operation.
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* GMII interface monitor with line-speed PTP packet parsing.
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* Variety of PTP packet formats supported.
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** L2 PTP packet, with stacked VLAN tags.
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** IPv4 and IPv6 UDP PTP packet, with stacked VLAN tags and/or stacked MPLS labels.
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* Configurable 8bit mask to selectively timestamp PTP event packet based on message type value.
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** 0: Sync
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** 1: Delay_Req
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** 2: Pdelay_Req
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** 3: Pdelay_Resp
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** 4 to 7: Reserved for future PTP event message types
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* 32bit packet parser datapath for easier timing closure.
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* 15-entry timestamp queue.
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* 15-entry timestamp queue.
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* 128bit timestamp format.
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* 128bit timestamp format.
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** 16bit extra information.
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** 16bit extra information.
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** 80bit timestamp.
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** 80bit timestamp.
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** 32bit packet identity data.
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** 32bit packet identity data.
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* GMII interface tap with line-speed PTP event packet parsing.
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** Sync
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** Delay_Req
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** Pdelay_Req
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** Pdelay_Resp
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* Variety of PTP packet formats support.
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** L2 PTP packet with stacked VLAN tags.
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** IPv4 and IPv6 UDP PTP packet with stacked VLAN tags and stacked MPLS labels.
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* 32bit internal datapath for easier timing closure.
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SystemVerilog DPI based simulation environment is included for SW driver development.
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SystemVerilog DPI based simulation environment is included for SW driver development and co-simulation.
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PCAP file based stimulus input is used for verification with real-world traffic.
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The IP Core can be used as an IP Component in Altera SOPC Builder. Example provided.
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The IP Core can be used as an IP Component in Altera SOPC Builder.
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The only FPGA vendor dependent module is the timestamp queue. This Altera DCFIFO can be replaced by any equivalent dual clock FIFO from other FPGA vendors.
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The only FPGA vendor dependent module is the timestamp queue. This Altera DCFIFO can be replaced by other FPGA vendor specific dual clock FIFO.
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