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[/] [ha1588/] [trunk/] [par/] [altera/] [ha1588.qsf] - Diff between revs 29 and 68

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Rev 29 Rev 68
Line 39... Line 39...
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY ha1588
set_global_assignment -name TOP_LEVEL_ENTITY ha1588
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.1 SP1"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:35:47  MARCH 31, 2012"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:35:47  MARCH 31, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1"
set_global_assignment -name LAST_QUARTUS_VERSION 12.1
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name SDC_FILE ha1588.sdc
set_global_assignment -name SDC_FILE ha1588.sdc
 
set_global_assignment -name SEARCH_PATH .\\ip
 
set_global_assignment -name VERILOG_FILE ./ip/dcfifo_128b_16.v
set_global_assignment -name VERILOG_FILE ../../rtl/top/ha1588.v
set_global_assignment -name VERILOG_FILE ../../rtl/top/ha1588.v
set_global_assignment -name VERILOG_FILE ../../rtl/rtc/rtc.v
set_global_assignment -name VERILOG_FILE ../../rtl/rtc/rtc.v
set_global_assignment -name VERILOG_FILE ../../rtl/reg/reg.v
set_global_assignment -name VERILOG_FILE ../../rtl/reg/reg.v
set_global_assignment -name VERILOG_FILE ../../rtl/tsu/tsu.v
set_global_assignment -name VERILOG_FILE ../../rtl/tsu/tsu.v
set_global_assignment -name VERILOG_FILE ../../rtl/tsu/ptp_queue.v
set_global_assignment -name VERILOG_FILE ../../rtl/tsu/ptp_queue.v
Line 60... Line 62...
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
 
 
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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