| Line 24... |
Line 24... |
input wire S_AXI_REG_WVALID,
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input wire S_AXI_REG_WVALID,
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output wire S_AXI_REG_WREADY,
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output wire S_AXI_REG_WREADY,
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// Register Slave Interface Write Response Ports
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// Register Slave Interface Write Response Ports
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output wire [2-1:0] S_AXI_REG_BRESP,
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output wire [2-1:0] S_AXI_REG_BRESP,
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output wire S_AXI_REG_BVALID,
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output reg S_AXI_REG_BVALID,
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input wire S_AXI_REG_BREADY,
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input wire S_AXI_REG_BREADY,
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// Register Slave Interface Read Address Ports
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// Register Slave Interface Read Address Ports
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input wire [C_S_AXI_REG_ADDR_WIDTH-1:0] S_AXI_REG_ARADDR,
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input wire [C_S_AXI_REG_ADDR_WIDTH-1:0] S_AXI_REG_ARADDR,
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input wire [3-1:0] S_AXI_REG_ARPROT,
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input wire [3-1:0] S_AXI_REG_ARPROT,
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| Line 76... |
Line 76... |
// TODO: to support read response channel holding
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// TODO: to support read response channel holding
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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assign S_AXI_REG_AWREADY = 1'b1;
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assign S_AXI_REG_AWREADY = 1'b1;
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assign S_AXI_REG_WREADY = 1'b1;
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assign S_AXI_REG_WREADY = 1'b1;
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assign S_AXI_REG_BRESP = 2'b00;
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assign S_AXI_REG_BRESP = 2'b00;
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assign S_AXI_REG_BVALID = S_AXI_REG_WVALID;
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always @(negedge S_AXI_REG_ARESETN or posedge S_AXI_REG_ACLK) begin
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if (!S_AXI_REG_ARESETN) S_AXI_REG_BVALID <= 1'b0;
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else S_AXI_REG_BVALID <= S_AXI_REG_WVALID;
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end
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assign S_AXI_REG_ARREADY = 1'b1;
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assign S_AXI_REG_ARREADY = 1'b1;
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assign S_AXI_REG_RDATA = up_data_rd;
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assign S_AXI_REG_RDATA = up_data_rd;
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assign S_AXI_REG_RRESP = 2'b00;
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assign S_AXI_REG_RRESP = 2'b00;
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always @(negedge S_AXI_REG_ARESETN or posedge S_AXI_REG_ACLK) begin
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always @(negedge S_AXI_REG_ARESETN or posedge S_AXI_REG_ACLK) begin
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if (!S_AXI_REG_ARESETN) S_AXI_REG_RVALID <= 1'b0;
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if (!S_AXI_REG_ARESETN) S_AXI_REG_RVALID <= 1'b0;
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