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[/] [ha1588/] [trunk/] [rtl/] [reg/] [reg.v] - Diff between revs 15 and 16
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Rev 16 |
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module reg (
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module reg (
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// generic bus interface
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input rst,clk,
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input wr_in,rd_in,
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input [ 3:0] addr_in,
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input [31:0] data_in,
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output [31:0] data_out,
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// rtc interface
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input rtc_rst,rtc_clk,
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output time_ld,
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output [37:0] time_reg_ns_out,
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output [47:0] time_reg_sec_out,
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output period_ld,
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output [39:0] period_out,
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output [37:0] time_acc_modulo_out,
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output adj_ld,
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output [31:0] adj_ld_data_out,
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output [39:0] period_adj_out,
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input [37:0] time_reg_ns_in,
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input [47:0] time_reg_sec_in,
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// tsu interface
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output q_rst,
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output q_rd_clk,
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output q_rd_en,
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input [ 7:0] q_rd_stat,
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input [55:0] q_rd_data
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);
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);
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endmodule
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endmodule
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