| Line 143... |
Line 143... |
reg [47:0] time_reg_sec_int;
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reg [47:0] time_reg_sec_int;
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reg [55:0] rx_q_data_int;
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reg [55:0] rx_q_data_int;
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reg [ 7:0] rx_q_stat_int;
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reg [ 7:0] rx_q_stat_int;
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reg [55:0] tx_q_data_int;
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reg [55:0] tx_q_data_int;
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reg [ 7:0] tx_q_stat_int;
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reg [ 7:0] tx_q_stat_int;
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reg time_ok;
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reg [31:0] data_out_reg;
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reg [31:0] data_out_reg;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rd_in && cs_00) data_out_reg <= reg_00;
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if (rd_in && cs_00) data_out_reg <= {reg_00[31:1], time_ok};
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if (rd_in && cs_04) data_out_reg <= {8'd0, rx_q_stat_int[ 7: 0], 8'd0, tx_q_stat_int[ 7: 0]};
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if (rd_in && cs_04) data_out_reg <= {8'd0, rx_q_stat_int[ 7: 0], 8'd0, tx_q_stat_int[ 7: 0]};
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if (rd_in && cs_08) data_out_reg <= reg_08;
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if (rd_in && cs_08) data_out_reg <= reg_08;
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if (rd_in && cs_0c) data_out_reg <= reg_0c;
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if (rd_in && cs_0c) data_out_reg <= reg_0c;
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if (rd_in && cs_10) data_out_reg <= reg_10;
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if (rd_in && cs_10) data_out_reg <= reg_10;
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if (rd_in && cs_14) data_out_reg <= reg_14;
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if (rd_in && cs_14) data_out_reg <= reg_14;
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| Line 194... |
Line 195... |
assign time_acc_modulo_out[37:0] = {reg_28[29: 0], reg_2c[ 7: 0]};
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assign time_acc_modulo_out[37:0] = {reg_28[29: 0], reg_2c[ 7: 0]};
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assign adj_ld_data_out [31:0] = reg_30[31: 0];
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assign adj_ld_data_out [31:0] = reg_30[31: 0];
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assign period_adj_out [39:0] = {reg_38[ 7: 0], reg_3c[31: 0]};
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assign period_adj_out [39:0] = {reg_38[ 7: 0], reg_3c[31: 0]};
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// real time clock
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// real time clock
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reg rtc_rst_d1, rtc_rst_d2, rtc_rst_d3;
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reg rtc_rst_s1, rtc_rst_s2, rtc_rst_s3;
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assign rtc_rst_out = rtc_rst_d2 && !rtc_rst_d3;
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assign rtc_rst_out = rtc_rst_s2 && !rtc_rst_s3;
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always @(posedge clk) begin
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always @(posedge rtc_clk_in) begin
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rtc_rst_d1 <= rtc_rst;
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rtc_rst_s1 <= rtc_rst;
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rtc_rst_d2 <= rtc_rst_d1;
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rtc_rst_s2 <= rtc_rst_s1;
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rtc_rst_d3 <= rtc_rst_d2;
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rtc_rst_s3 <= rtc_rst_s2;
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end
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end
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reg time_ld_d1, time_ld_d2, time_ld_d3;
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reg time_ld_s1, time_ld_s2, time_ld_s3;
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assign time_ld_out = time_ld_d2 && !time_ld_d3;
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assign time_ld_out = time_ld_s2 && !time_ld_s3;
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always @(posedge clk) begin
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always @(posedge rtc_clk_in) begin
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time_ld_d1 <= time_ld;
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time_ld_s1 <= time_ld;
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time_ld_d2 <= time_ld_d1;
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time_ld_s2 <= time_ld_s1;
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time_ld_d3 <= time_ld_d2;
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time_ld_s3 <= time_ld_s2;
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end
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end
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reg perd_ld_d1, perd_ld_d2, perd_ld_d3;
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reg perd_ld_s1, perd_ld_s2, perd_ld_s3;
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assign period_ld_out = perd_ld_d2 && !perd_ld_d3;
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assign period_ld_out = perd_ld_s2 && !perd_ld_s3;
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always @(posedge clk) begin
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always @(posedge rtc_clk_in) begin
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perd_ld_d1 <= perd_ld;
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perd_ld_s1 <= perd_ld;
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perd_ld_d2 <= perd_ld_d1;
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perd_ld_s2 <= perd_ld_s1;
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perd_ld_d3 <= perd_ld_d2;
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perd_ld_s3 <= perd_ld_s2;
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end
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end
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reg adjt_ld_d1, adjt_ld_d2, adjt_ld_d3;
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reg adjt_ld_s1, adjt_ld_s2, adjt_ld_s3;
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assign adj_ld_out = adjt_ld_d2 && !adjt_ld_d3;
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assign adj_ld_out = adjt_ld_s2 && !adjt_ld_s3;
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always @(posedge clk) begin
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always @(posedge rtc_clk_in) begin
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adjt_ld_d1 <= adjt_ld;
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adjt_ld_s1 <= adjt_ld;
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adjt_ld_d2 <= adjt_ld_d1;
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adjt_ld_s2 <= adjt_ld_s1;
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adjt_ld_d3 <= adjt_ld_d2;
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adjt_ld_s3 <= adjt_ld_s2;
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end
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end
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reg time_rd_d1, time_rd_d2, time_rd_d3;
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// RTC time read CDC hand-shaking
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wire time_reg_in_latch = time_rd_d2 && !time_rd_d3;
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reg time_rd_s1, time_rd_s2, time_rd_s3;
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wire time_rd_ack = time_rd_s2 && !time_rd_s3;
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always @(posedge rtc_clk_in) begin
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always @(posedge rtc_clk_in) begin
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time_rd_d1 <= time_rd;
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time_rd_s1 <= time_rd;
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time_rd_d2 <= time_rd_d1;
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time_rd_s2 <= time_rd_s1;
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time_rd_d3 <= time_rd_d2;
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time_rd_s3 <= time_rd_s2;
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end
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end
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always @(posedge rtc_clk_in) begin
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always @(posedge rtc_clk_in) begin
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if (time_reg_in_latch) begin
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if (time_rd_ack) begin
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time_reg_ns_int <= time_reg_ns_in;
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time_reg_ns_int <= time_reg_ns_in;
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time_reg_sec_int <= time_reg_sec_in;
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time_reg_sec_int <= time_reg_sec_in;
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end
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end
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end
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end
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reg time_rd_d1;
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wire time_rd_req = time_rd && !time_rd_d1;
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always @(posedge clk) begin
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time_rd_d1 <= time_rd;
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end
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always @(posedge clk or posedge time_rd_ack) begin
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if (time_rd_ack)
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time_ok <= 1'b1;
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else if (time_rd_req)
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time_ok <= 1'b0;
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end
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// rx time stamp queue
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// rx time stamp queue
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assign rx_q_rd_clk_out = clk;
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assign rx_q_rd_clk_out = clk;
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reg rxq_rst_d1, rxq_rst_d2, rxq_rst_d3;
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reg rxq_rst_d1, rxq_rst_d2, rxq_rst_d3;
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assign rx_q_rst_out = rxq_rst_d2 && !rxq_rst_d3;
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assign rx_q_rst_out = rxq_rst_d2 && !rxq_rst_d3;
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