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https://opencores.org/ocsvn/ha1588/ha1588/trunk
[/] [ha1588/] [trunk/] [rtl/] [reg/] [reg.v] - Diff between revs 23 and 24
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| Rev 23 |
Rev 24 |
| Line 148... |
Line 148... |
reg time_ok;
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reg time_ok;
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reg [31:0] data_out_reg;
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reg [31:0] data_out_reg;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rd_in && cs_00) data_out_reg <= {reg_00[31:1], time_ok};
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if (rd_in && cs_00) data_out_reg <= {reg_00[31:1], time_ok};
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if (rd_in && cs_04) data_out_reg <= {8'd0, rx_q_stat_int[ 7: 0], 8'd0, tx_q_stat_int[ 7: 0]};
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if (rd_in && cs_04) data_out_reg <= {24'd0, rx_q_stat_int[ 7: 0]};
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if (rd_in && cs_08) data_out_reg <= reg_08;
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if (rd_in && cs_08) data_out_reg <= {24'd0, tx_q_stat_int[ 7: 0]};
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if (rd_in && cs_0c) data_out_reg <= reg_0c;
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if (rd_in && cs_0c) data_out_reg <= reg_0c;
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if (rd_in && cs_10) data_out_reg <= reg_10;
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if (rd_in && cs_10) data_out_reg <= reg_10;
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if (rd_in && cs_14) data_out_reg <= reg_14;
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if (rd_in && cs_14) data_out_reg <= reg_14;
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if (rd_in && cs_18) data_out_reg <= reg_18;
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if (rd_in && cs_18) data_out_reg <= reg_18;
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if (rd_in && cs_1c) data_out_reg <= reg_1c;
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if (rd_in && cs_1c) data_out_reg <= reg_1c;
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