| Line 24... |
Line 24... |
// rx tsu interface
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// rx tsu interface
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output rx_q_rst_out,
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output rx_q_rst_out,
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output rx_q_rd_clk_out,
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output rx_q_rd_clk_out,
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output rx_q_rd_en_out,
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output rx_q_rd_en_out,
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input [ 7:0] rx_q_stat_in,
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input [ 7:0] rx_q_stat_in,
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input [55:0] rx_q_data_in,
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input [63:0] rx_q_data_in,
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// tx tsu interface
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// tx tsu interface
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output tx_q_rst_out,
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output tx_q_rst_out,
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output tx_q_rd_clk_out,
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output tx_q_rd_clk_out,
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output tx_q_rd_en_out,
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output tx_q_rd_en_out,
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input [ 7:0] tx_q_stat_in,
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input [ 7:0] tx_q_stat_in,
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input [55:0] tx_q_data_in
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input [63:0] tx_q_data_in
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);
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);
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|
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parameter const_00 = 8'h00;
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parameter const_00 = 8'h00;
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parameter const_04 = 8'h04;
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parameter const_04 = 8'h04;
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parameter const_08 = 8'h08;
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parameter const_08 = 8'h08;
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| Line 139... |
Line 139... |
end
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end
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|
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// read registers
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// read registers
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reg [37:0] time_reg_ns_int;
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reg [37:0] time_reg_ns_int;
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reg [47:0] time_reg_sec_int;
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reg [47:0] time_reg_sec_int;
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reg [55:0] rx_q_data_int;
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reg [63:0] rx_q_data_int;
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reg [ 7:0] rx_q_stat_int;
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reg [ 7:0] rx_q_stat_int;
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reg [55:0] tx_q_data_int;
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reg [63:0] tx_q_data_int;
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reg [ 7:0] tx_q_stat_int;
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reg [ 7:0] tx_q_stat_int;
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reg time_ok;
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reg time_ok;
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|
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reg [31:0] data_out_reg;
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reg [31:0] data_out_reg;
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always @(posedge clk) begin
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always @(posedge clk) begin
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| Line 167... |
Line 167... |
if (rd_in && cs_3c) data_out_reg <= reg_3c;
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if (rd_in && cs_3c) data_out_reg <= reg_3c;
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if (rd_in && cs_40) data_out_reg <= {16'd0, time_reg_sec_int[47:32]};
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if (rd_in && cs_40) data_out_reg <= {16'd0, time_reg_sec_int[47:32]};
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if (rd_in && cs_44) data_out_reg <= time_reg_sec_int[31: 0];
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if (rd_in && cs_44) data_out_reg <= time_reg_sec_int[31: 0];
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if (rd_in && cs_48) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]};
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if (rd_in && cs_48) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]};
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if (rd_in && cs_4c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]};
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if (rd_in && cs_4c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]};
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if (rd_in && cs_50) data_out_reg <= { 8'd0, rx_q_data_int[55:32]};
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if (rd_in && cs_50) data_out_reg <= rx_q_data_int[63:32];
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if (rd_in && cs_54) data_out_reg <= rx_q_data_int[31: 0];
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if (rd_in && cs_54) data_out_reg <= rx_q_data_int[31: 0];
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if (rd_in && cs_58) data_out_reg <= { 8'd0, tx_q_data_int[55:32]};
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if (rd_in && cs_58) data_out_reg <= tx_q_data_int[63:32];
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if (rd_in && cs_5c) data_out_reg <= tx_q_data_int[31: 0];
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if (rd_in && cs_5c) data_out_reg <= tx_q_data_int[31: 0];
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end
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end
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assign data_out = data_out_reg;
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assign data_out = data_out_reg;
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|
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// register mapping
|
// register mapping
|
