| Line 144... |
Line 144... |
reg [63:0] rx_q_data_int;
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reg [63:0] rx_q_data_int;
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reg [ 7:0] rx_q_stat_int;
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reg [ 7:0] rx_q_stat_int;
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reg [63:0] tx_q_data_int;
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reg [63:0] tx_q_data_int;
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reg [ 7:0] tx_q_stat_int;
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reg [ 7:0] tx_q_stat_int;
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reg time_ok;
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reg time_ok;
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reg rxqu_ok;
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reg txqu_ok;
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reg [31:0] data_out_reg;
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reg [31:0] data_out_reg;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rd_in && cs_00) data_out_reg <= {reg_00[31:1], time_ok};
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if (rd_in && cs_00) data_out_reg <= {reg_00[31:12], reg_00[11], rxqu_ok, reg_00[9], txqu_ok, reg_00[ 7: 1], time_ok};
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if (rd_in && cs_04) data_out_reg <= {24'd0, rx_q_stat_int[ 7: 0]};
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if (rd_in && cs_04) data_out_reg <= {24'd0, rx_q_stat_int[ 7: 0]};
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if (rd_in && cs_08) data_out_reg <= {24'd0, tx_q_stat_int[ 7: 0]};
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if (rd_in && cs_08) data_out_reg <= {24'd0, tx_q_stat_int[ 7: 0]};
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if (rd_in && cs_0c) data_out_reg <= reg_0c;
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if (rd_in && cs_0c) data_out_reg <= reg_0c;
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if (rd_in && cs_10) data_out_reg <= reg_10;
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if (rd_in && cs_10) data_out_reg <= reg_10;
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if (rd_in && cs_14) data_out_reg <= reg_14;
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if (rd_in && cs_14) data_out_reg <= reg_14;
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| Line 267... |
Line 269... |
rxq_rst_d1 <= rxq_rst;
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rxq_rst_d1 <= rxq_rst;
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rxq_rst_d2 <= rxq_rst_d1;
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rxq_rst_d2 <= rxq_rst_d1;
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rxq_rst_d3 <= rxq_rst_d2;
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rxq_rst_d3 <= rxq_rst_d2;
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end
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end
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reg rxqu_rd_d1, rxqu_rd_d2, rxqu_rd_d3;
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reg rxqu_rd_d1, rxqu_rd_d2, rxqu_rd_d3, rxqu_rd_d4, rxqu_rd_d5;
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assign rx_q_rd_en_out = rxqu_rd_d2 && !rxqu_rd_d3;
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assign rx_q_rd_en_out = rxqu_rd_d2 && !rxqu_rd_d3;
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wire rx_q_rd_req = rxqu_rd_d2 && !rxqu_rd_d3;
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wire rx_q_rd_ack = rxqu_rd_d4 && !rxqu_rd_d5;
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always @(posedge clk) begin
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always @(posedge clk) begin
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rxqu_rd_d1 <= rxqu_rd;
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rxqu_rd_d1 <= rxqu_rd;
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rxqu_rd_d2 <= rxqu_rd_d1;
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rxqu_rd_d2 <= rxqu_rd_d1;
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rxqu_rd_d3 <= rxqu_rd_d2;
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rxqu_rd_d3 <= rxqu_rd_d2;
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rxqu_rd_d4 <= rxqu_rd_d3;
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rxqu_rd_d5 <= rxqu_rd_d4;
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end
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always @(posedge clk) begin
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if (rx_q_rd_ack)
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rxqu_ok <= 1'b1;
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else if (rx_q_rd_req)
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rxqu_ok <= 1'b0;
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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rx_q_data_int <= rx_q_data_in;
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rx_q_data_int <= rx_q_data_in;
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rx_q_stat_int <= rx_q_stat_in;
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rx_q_stat_int <= rx_q_stat_in;
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| Line 291... |
Line 304... |
txq_rst_d1 <= txq_rst;
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txq_rst_d1 <= txq_rst;
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txq_rst_d2 <= txq_rst_d1;
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txq_rst_d2 <= txq_rst_d1;
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txq_rst_d3 <= txq_rst_d2;
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txq_rst_d3 <= txq_rst_d2;
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end
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end
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reg txqu_rd_d1, txqu_rd_d2, txqu_rd_d3;
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reg txqu_rd_d1, txqu_rd_d2, txqu_rd_d3, txqu_rd_d4, txqu_rd_d5;
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assign tx_q_rd_en_out = txqu_rd_d2 && !txqu_rd_d3;
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assign tx_q_rd_en_out = txqu_rd_d2 && !txqu_rd_d3;
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wire tx_q_rd_req = txqu_rd_d2 && !txqu_rd_d3;
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wire tx_q_rd_ack = txqu_rd_d4 && !txqu_rd_d5;
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always @(posedge clk) begin
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always @(posedge clk) begin
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txqu_rd_d1 <= txqu_rd;
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txqu_rd_d1 <= txqu_rd;
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txqu_rd_d2 <= txqu_rd_d1;
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txqu_rd_d2 <= txqu_rd_d1;
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txqu_rd_d3 <= txqu_rd_d2;
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txqu_rd_d3 <= txqu_rd_d2;
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txqu_rd_d4 <= txqu_rd_d3;
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txqu_rd_d5 <= txqu_rd_d4;
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end
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always @(posedge clk) begin
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if (tx_q_rd_ack)
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txqu_ok <= 1'b1;
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else if (tx_q_rd_req)
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txqu_ok <= 1'b0;
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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tx_q_data_int <= tx_q_data_in;
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tx_q_data_int <= tx_q_data_in;
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tx_q_stat_int <= tx_q_stat_in;
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tx_q_stat_int <= tx_q_stat_in;
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