| Line 57... |
Line 57... |
parameter const_4c = 8'h4C;
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parameter const_4c = 8'h4C;
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parameter const_50 = 8'h50;
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parameter const_50 = 8'h50;
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parameter const_54 = 8'h54;
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parameter const_54 = 8'h54;
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parameter const_58 = 8'h58;
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parameter const_58 = 8'h58;
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parameter const_5c = 8'h5C;
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parameter const_5c = 8'h5C;
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parameter const_60 = 8'h60;
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parameter const_64 = 8'h64;
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parameter const_68 = 8'h68;
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parameter const_6c = 8'h6C;
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wire cs_00 = (addr_in[7:2]==const_00[7:2])? 1'b1: 1'b0;
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wire cs_00 = (addr_in[7:2]==const_00[7:2])? 1'b1: 1'b0;
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wire cs_04 = (addr_in[7:2]==const_04[7:2])? 1'b1: 1'b0;
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wire cs_04 = (addr_in[7:2]==const_04[7:2])? 1'b1: 1'b0;
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wire cs_08 = (addr_in[7:2]==const_08[7:2])? 1'b1: 1'b0;
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wire cs_08 = (addr_in[7:2]==const_08[7:2])? 1'b1: 1'b0;
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wire cs_0c = (addr_in[7:2]==const_0c[7:2])? 1'b1: 1'b0;
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wire cs_0c = (addr_in[7:2]==const_0c[7:2])? 1'b1: 1'b0;
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| Line 82... |
Line 86... |
wire cs_4c = (addr_in[7:2]==const_4c[7:2])? 1'b1: 1'b0;
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wire cs_4c = (addr_in[7:2]==const_4c[7:2])? 1'b1: 1'b0;
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wire cs_50 = (addr_in[7:2]==const_50[7:2])? 1'b1: 1'b0;
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wire cs_50 = (addr_in[7:2]==const_50[7:2])? 1'b1: 1'b0;
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wire cs_54 = (addr_in[7:2]==const_54[7:2])? 1'b1: 1'b0;
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wire cs_54 = (addr_in[7:2]==const_54[7:2])? 1'b1: 1'b0;
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wire cs_58 = (addr_in[7:2]==const_58[7:2])? 1'b1: 1'b0;
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wire cs_58 = (addr_in[7:2]==const_58[7:2])? 1'b1: 1'b0;
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wire cs_5c = (addr_in[7:2]==const_5c[7:2])? 1'b1: 1'b0;
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wire cs_5c = (addr_in[7:2]==const_5c[7:2])? 1'b1: 1'b0;
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wire cs_60 = (addr_in[7:2]==const_60[7:2])? 1'b1: 1'b0;
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wire cs_64 = (addr_in[7:2]==const_64[7:2])? 1'b1: 1'b0;
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wire cs_68 = (addr_in[7:2]==const_68[7:2])? 1'b1: 1'b0;
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wire cs_6c = (addr_in[7:2]==const_6c[7:2])? 1'b1: 1'b0;
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reg [31:0] reg_00; // ctrl 12 bit
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reg [31:0] reg_00; // ctrl 5 bit
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reg [31:0] reg_04; // qsta 16 bit
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reg [31:0] reg_04; //
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reg [31:0] reg_08; //
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reg [31:0] reg_08; //
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reg [31:0] reg_0c; //
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reg [31:0] reg_0c; //
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reg [31:0] reg_10; // tout 16 s
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reg [31:0] reg_10; // tout 16 s
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reg [31:0] reg_14; // tout 32 s
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reg [31:0] reg_14; // tout 32 s
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reg [31:0] reg_18; // tout 30 ns
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reg [31:0] reg_18; // tout 30 ns
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| Line 103... |
Line 111... |
reg [31:0] reg_3c; // ajpr 32 nsf
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reg [31:0] reg_3c; // ajpr 32 nsf
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reg [31:0] reg_40; // tmin 16 s
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reg [31:0] reg_40; // tmin 16 s
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reg [31:0] reg_44; // tmin 32 s
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reg [31:0] reg_44; // tmin 32 s
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reg [31:0] reg_48; // tmin 30 ns
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reg [31:0] reg_48; // tmin 30 ns
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reg [31:0] reg_4c; // tmin 8 nsf
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reg [31:0] reg_4c; // tmin 8 nsf
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reg [31:0] reg_50; // rxqu 24 bit
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reg [31:0] reg_50; // ctrl 4 bit
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reg [31:0] reg_54; // rxqu 32 bit
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reg [31:0] reg_54; // qsta 8 bit
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reg [31:0] reg_58; // txqu 24 bit
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reg [31:0] reg_58; // qsta 8 bit
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reg [31:0] reg_5c; // txqu 32 bit
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reg [31:0] reg_5c; //
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reg [31:0] reg_60; // rxqu 32 bit
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reg [31:0] reg_64; // rxqu 32 bit
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reg [31:0] reg_68; // txqu 32 bit
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reg [31:0] reg_6c; // txqu 32 bit
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// write registers
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// write registers
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (wr_in && cs_00) reg_00 <= data_in;
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if (wr_in && cs_00) reg_00 <= data_in;
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if (wr_in && cs_04) reg_04 <= data_in;
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if (wr_in && cs_04) reg_04 <= data_in;
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| Line 134... |
Line 146... |
if (wr_in && cs_4c) reg_4c <= data_in;
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if (wr_in && cs_4c) reg_4c <= data_in;
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if (wr_in && cs_50) reg_50 <= data_in;
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if (wr_in && cs_50) reg_50 <= data_in;
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if (wr_in && cs_54) reg_54 <= data_in;
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if (wr_in && cs_54) reg_54 <= data_in;
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if (wr_in && cs_58) reg_58 <= data_in;
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if (wr_in && cs_58) reg_58 <= data_in;
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if (wr_in && cs_5c) reg_5c <= data_in;
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if (wr_in && cs_5c) reg_5c <= data_in;
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if (wr_in && cs_60) reg_60 <= data_in;
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if (wr_in && cs_64) reg_64 <= data_in;
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if (wr_in && cs_68) reg_68 <= data_in;
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if (wr_in && cs_6c) reg_6c <= data_in;
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end
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end
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// read registers
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// read registers
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reg [37:0] time_reg_ns_int;
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reg [37:0] time_reg_ns_int;
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reg [47:0] time_reg_sec_int;
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reg [47:0] time_reg_sec_int;
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| Line 149... |
Line 165... |
reg rxqu_ok;
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reg rxqu_ok;
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reg txqu_ok;
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reg txqu_ok;
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reg [31:0] data_out_reg;
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reg [31:0] data_out_reg;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rd_in && cs_00) data_out_reg <= {reg_00[31:12], reg_00[11], rxqu_ok, reg_00[9], txqu_ok, reg_00[ 7: 1], time_ok};
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if (rd_in && cs_00) data_out_reg <= {reg_00[31:1 ], time_ok};
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if (rd_in && cs_04) data_out_reg <= {24'd0, rx_q_stat_int[ 7: 0]};
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if (rd_in && cs_04) data_out_reg <= reg_04;
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if (rd_in && cs_08) data_out_reg <= {24'd0, tx_q_stat_int[ 7: 0]};
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if (rd_in && cs_08) data_out_reg <= reg_08;
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if (rd_in && cs_0c) data_out_reg <= reg_0c;
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if (rd_in && cs_0c) data_out_reg <= reg_0c;
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if (rd_in && cs_10) data_out_reg <= reg_10;
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if (rd_in && cs_10) data_out_reg <= reg_10;
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if (rd_in && cs_14) data_out_reg <= reg_14;
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if (rd_in && cs_14) data_out_reg <= reg_14;
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if (rd_in && cs_18) data_out_reg <= reg_18;
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if (rd_in && cs_18) data_out_reg <= reg_18;
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if (rd_in && cs_1c) data_out_reg <= reg_1c;
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if (rd_in && cs_1c) data_out_reg <= reg_1c;
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| Line 169... |
Line 185... |
if (rd_in && cs_3c) data_out_reg <= reg_3c;
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if (rd_in && cs_3c) data_out_reg <= reg_3c;
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if (rd_in && cs_40) data_out_reg <= {16'd0, time_reg_sec_int[47:32]};
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if (rd_in && cs_40) data_out_reg <= {16'd0, time_reg_sec_int[47:32]};
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if (rd_in && cs_44) data_out_reg <= time_reg_sec_int[31: 0];
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if (rd_in && cs_44) data_out_reg <= time_reg_sec_int[31: 0];
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if (rd_in && cs_48) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]};
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if (rd_in && cs_48) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]};
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if (rd_in && cs_4c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]};
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if (rd_in && cs_4c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]};
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if (rd_in && cs_50) data_out_reg <= rx_q_data_int[63:32];
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if (rd_in && cs_50) data_out_reg <= {reg_50[31: 4], reg_50[ 3], rxqu_ok, reg_50[ 1], txqu_ok};
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if (rd_in && cs_54) data_out_reg <= rx_q_data_int[31: 0];
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if (rd_in && cs_54) data_out_reg <= {24'd0, rx_q_stat_int[ 7: 0]};
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if (rd_in && cs_58) data_out_reg <= tx_q_data_int[63:32];
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if (rd_in && cs_58) data_out_reg <= {24'd0, tx_q_stat_int[ 7: 0]};
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if (rd_in && cs_5c) data_out_reg <= tx_q_data_int[31: 0];
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if (rd_in && cs_5c) data_out_reg <= reg_5c;
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if (rd_in && cs_60) data_out_reg <= rx_q_data_int[63:32];
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if (rd_in && cs_64) data_out_reg <= rx_q_data_int[31: 0];
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if (rd_in && cs_68) data_out_reg <= tx_q_data_int[63:32];
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if (rd_in && cs_6c) data_out_reg <= tx_q_data_int[31: 0];
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end
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end
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assign data_out = data_out_reg;
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assign data_out = data_out_reg;
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// register mapping
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// register mapping: RTC
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wire rxq_rst = reg_00[11];
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wire rxqu_rd = reg_00[10];
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wire txq_rst = reg_00[ 9];
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wire txqu_rd = reg_00[ 8];
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//wire = reg_00[ 7];
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//wire = reg_00[ 7];
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//wire = reg_00[ 6];
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//wire = reg_00[ 6];
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//wire = reg_00[ 5];
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//wire = reg_00[ 5];
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wire rtc_rst = reg_00[ 4];
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wire rtc_rst = reg_00[ 4];
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wire time_ld = reg_00[ 3];
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wire time_ld = reg_00[ 3];
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| Line 195... |
Line 211... |
assign time_reg_ns_out [37:0] = {reg_18[29: 0], reg_1c[ 7: 0]};
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assign time_reg_ns_out [37:0] = {reg_18[29: 0], reg_1c[ 7: 0]};
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assign period_out [39:0] = {reg_20[ 7: 0], reg_24[31: 0]};
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assign period_out [39:0] = {reg_20[ 7: 0], reg_24[31: 0]};
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assign time_acc_modulo_out[37:0] = {reg_28[29: 0], reg_2c[ 7: 0]};
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assign time_acc_modulo_out[37:0] = {reg_28[29: 0], reg_2c[ 7: 0]};
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assign adj_ld_data_out [31:0] = reg_30[31: 0];
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assign adj_ld_data_out [31:0] = reg_30[31: 0];
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assign period_adj_out [39:0] = {reg_38[ 7: 0], reg_3c[31: 0]};
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assign period_adj_out [39:0] = {reg_38[ 7: 0], reg_3c[31: 0]};
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// register mapping: TSU
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//wire = reg_50[ 7];
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//wire = reg_50[ 6];
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//wire = reg_50[ 5];
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//wire = reg_50[ 4];
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wire rxq_rst = reg_50[ 3];
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wire rxqu_rd = reg_50[ 2];
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wire txq_rst = reg_50[ 1];
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wire txqu_rd = reg_50[ 0];
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// real time clock
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// real time clock
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reg rtc_rst_s1, rtc_rst_s2, rtc_rst_s3;
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reg rtc_rst_s1, rtc_rst_s2, rtc_rst_s3;
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assign rtc_rst_out = rtc_rst_s2 && !rtc_rst_s3;
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assign rtc_rst_out = rtc_rst_s2 && !rtc_rst_s3;
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always @(posedge rtc_clk_in) begin
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always @(posedge rtc_clk_in) begin
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