| Line 124... |
Line 124... |
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reg [31:0] reg_00; // ctrl 5 bit
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reg [31:0] reg_00; // ctrl 5 bit
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reg [31:0] reg_04; // null
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reg [31:0] reg_04; // null
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reg [31:0] reg_08; // null
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reg [31:0] reg_08; // null
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reg [31:0] reg_0c; // null
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reg [31:0] reg_0c; // null
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reg [31:0] reg_10; // time 16 s
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reg [31:0] reg_10; // time 16 bit s
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reg [31:0] reg_14; // time 32 s
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reg [31:0] reg_14; // time 32 bit s
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reg [31:0] reg_18; // time 30 ns
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reg [31:0] reg_18; // time 30 bit ns
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reg [31:0] reg_1c; // time 8 nsf
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reg [31:0] reg_1c; // time 8 bit nsf
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reg [31:0] reg_20; // peri 8 ns
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reg [31:0] reg_20; // peri 8 bit ns
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reg [31:0] reg_24; // peri 32 nsf
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reg [31:0] reg_24; // peri 32 bit nsf
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reg [31:0] reg_28; // ajpr 8 ns
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reg [31:0] reg_28; // ajpr 8 bit ns
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reg [31:0] reg_2c; // ajpr 32 nsf
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reg [31:0] reg_2c; // ajpr 32 bit nsf
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reg [31:0] reg_30; // ajld 32 bit
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reg [31:0] reg_30; // ajld 32 bit
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reg [31:0] reg_34; // null
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reg [31:0] reg_34; // null
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reg [31:0] reg_38; // null
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reg [31:0] reg_38; // null
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reg [31:0] reg_3c; // null
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reg [31:0] reg_3c; // null
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reg [31:0] reg_40; // ctrl 4 bit
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reg [31:0] reg_40; // ctrl 2 bit
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reg [31:0] reg_44; // qsta 8 bit
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reg [31:0] reg_44; // qsta 8 bit
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reg [31:0] reg_48; // qsta 8 bit
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reg [31:0] reg_48; // null
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reg [31:0] reg_4c; // null
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reg [31:0] reg_4c; // null
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reg [31:0] reg_50; // null
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reg [31:0] reg_50; // rxqu 32 bit
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reg [31:0] reg_54; // null
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reg [31:0] reg_54; // rxqu 32 bit
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reg [31:0] reg_58; // null
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reg [31:0] reg_58; // rxqu 32 bit
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reg [31:0] reg_5c; // null
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reg [31:0] reg_5c; // rxqu 32 bit
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reg [31:0] reg_60; // rxqu 32 bit
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reg [31:0] reg_60; // ctrl 2 bit
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reg [31:0] reg_64; // rxqu 32 bit
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reg [31:0] reg_64; // qsta 8 bit
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reg [31:0] reg_68; // rxqu 32 bit
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reg [31:0] reg_68; // null
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reg [31:0] reg_6c; // rxqu 32 bit
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reg [31:0] reg_6c; // null
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reg [31:0] reg_70; // txqu 32 bit
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reg [31:0] reg_70; // txqu 32 bit
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reg [31:0] reg_74; // txqu 32 bit
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reg [31:0] reg_74; // txqu 32 bit
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reg [31:0] reg_78; // txqu 32 bit
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reg [31:0] reg_78; // txqu 32 bit
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reg [31:0] reg_7c; // txqu 32 bit
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reg [31:0] reg_7c; // txqu 32 bit
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| Line 219... |
Line 219... |
if (rd_in && cs_2c) data_out_reg <= reg_2c;
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if (rd_in && cs_2c) data_out_reg <= reg_2c;
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if (rd_in && cs_30) data_out_reg <= reg_30;
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if (rd_in && cs_30) data_out_reg <= reg_30;
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if (rd_in && cs_34) data_out_reg <= reg_34;
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if (rd_in && cs_34) data_out_reg <= reg_34;
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if (rd_in && cs_38) data_out_reg <= reg_38;
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if (rd_in && cs_38) data_out_reg <= reg_38;
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if (rd_in && cs_3c) data_out_reg <= reg_3c;
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if (rd_in && cs_3c) data_out_reg <= reg_3c;
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// register mapping: TSU
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// register mapping: TSU RX
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if (rd_in && cs_40) data_out_reg <= {reg_40[31: 4], reg_40[ 3], rxqu_ok, reg_40[ 1], txqu_ok};
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if (rd_in && cs_40) data_out_reg <= {reg_40[31: 2], reg_40[ 1], rxqu_ok};
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if (rd_in && cs_44) data_out_reg <= {24'd0, rx_q_stat_int[ 7: 0]};
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if (rd_in && cs_44) data_out_reg <= {24'd0, rx_q_stat_int[ 7: 0]};
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if (rd_in && cs_48) data_out_reg <= {24'd0, tx_q_stat_int[ 7: 0]};
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if (rd_in && cs_48) data_out_reg <= reg_48;
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if (rd_in && cs_4c) data_out_reg <= reg_4c;
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if (rd_in && cs_4c) data_out_reg <= reg_4c;
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if (rd_in && cs_50) data_out_reg <= reg_50;
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if (rd_in && cs_50) data_out_reg <= rx_q_data_int[127: 96];
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if (rd_in && cs_54) data_out_reg <= reg_54;
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if (rd_in && cs_54) data_out_reg <= rx_q_data_int[ 95: 64];
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if (rd_in && cs_58) data_out_reg <= reg_58;
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if (rd_in && cs_58) data_out_reg <= rx_q_data_int[ 63: 32];
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if (rd_in && cs_5c) data_out_reg <= reg_5c;
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if (rd_in && cs_5c) data_out_reg <= rx_q_data_int[ 31: 0];
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if (rd_in && cs_60) data_out_reg <= rx_q_data_int[127: 96];
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// register mapping: TSU TX
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if (rd_in && cs_64) data_out_reg <= rx_q_data_int[ 95: 64];
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if (rd_in && cs_60) data_out_reg <= {reg_60[31: 2], reg_60[ 1], txqu_ok};
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if (rd_in && cs_68) data_out_reg <= rx_q_data_int[ 63: 32];
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if (rd_in && cs_64) data_out_reg <= {24'd0, tx_q_stat_int[ 7: 0]};
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if (rd_in && cs_6c) data_out_reg <= rx_q_data_int[ 31: 0];
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if (rd_in && cs_68) data_out_reg <= reg_68;
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if (rd_in && cs_6c) data_out_reg <= reg_6c;
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if (rd_in && cs_70) data_out_reg <= tx_q_data_int[127: 96];
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if (rd_in && cs_70) data_out_reg <= tx_q_data_int[127: 96];
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if (rd_in && cs_74) data_out_reg <= tx_q_data_int[ 95: 64];
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if (rd_in && cs_74) data_out_reg <= tx_q_data_int[ 95: 64];
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if (rd_in && cs_78) data_out_reg <= tx_q_data_int[ 63: 32];
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if (rd_in && cs_78) data_out_reg <= tx_q_data_int[ 63: 32];
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if (rd_in && cs_7c) data_out_reg <= tx_q_data_int[ 31: 0];
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if (rd_in && cs_7c) data_out_reg <= tx_q_data_int[ 31: 0];
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end
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end
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| Line 254... |
Line 255... |
assign time_reg_ns_out [37:0] = {reg_18[29: 0], reg_1c[ 7: 0]};
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assign time_reg_ns_out [37:0] = {reg_18[29: 0], reg_1c[ 7: 0]};
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assign period_out [39:0] = {reg_20[ 7: 0], reg_24[31: 0]};
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assign period_out [39:0] = {reg_20[ 7: 0], reg_24[31: 0]};
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assign period_adj_out [39:0] = {reg_28[ 7: 0], reg_2c[31: 0]};
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assign period_adj_out [39:0] = {reg_28[ 7: 0], reg_2c[31: 0]};
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assign adj_ld_data_out [31:0] = reg_30[31: 0];
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assign adj_ld_data_out [31:0] = reg_30[31: 0];
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// register mapping: TSU
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// register mapping: TSU RX
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//wire = reg_40[ 7];
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//wire = reg_40[ 7];
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//wire = reg_40[ 6];
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//wire = reg_40[ 6];
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//wire = reg_40[ 5];
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//wire = reg_40[ 5];
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//wire = reg_40[ 4];
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//wire = reg_40[ 4];
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wire rxq_rst = reg_40[ 3];
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//wire = reg_40[ 3];
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wire rxqu_rd = reg_40[ 2];
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//wire = reg_40[ 2];
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wire txq_rst = reg_40[ 1];
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wire rxq_rst = reg_40[ 1];
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wire txqu_rd = reg_40[ 0];
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wire rxqu_rd = reg_40[ 0];
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// register mapping: TSU TX
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//wire = reg_60[ 7];
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//wire = reg_60[ 6];
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//wire = reg_60[ 5];
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//wire = reg_60[ 4];
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//wire = reg_60[ 3];
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//wire = reg_60[ 2];
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wire txq_rst = reg_60[ 1];
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wire txqu_rd = reg_60[ 0];
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// TODO: add configurable PTP Event msgID value mask
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// TODO: add configurable VLANTPID values
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// TODO: add configurable VLANTPID values
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// real time clock
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// real time clock
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reg rtc_rst_s1, rtc_rst_s2, rtc_rst_s3;
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reg rtc_rst_s1, rtc_rst_s2, rtc_rst_s3;
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assign rtc_rst_out = rtc_rst_s2 && !rtc_rst_s3;
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assign rtc_rst_out = rtc_rst_s2 && !rtc_rst_s3;
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