| Line 44... |
Line 44... |
input [47:0] time_reg_sec_in,
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input [47:0] time_reg_sec_in,
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// rx tsu interface
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// rx tsu interface
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output rx_q_rst_out,
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output rx_q_rst_out,
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output rx_q_rd_clk_out,
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output rx_q_rd_clk_out,
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output rx_q_rd_en_out,
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output rx_q_rd_en_out,
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output [ 7:0] rx_q_ptp_msgid_mask_out,
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input [ 7:0] rx_q_stat_in,
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input [ 7:0] rx_q_stat_in,
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input [127:0] rx_q_data_in,
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input [127:0] rx_q_data_in,
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// tx tsu interface
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// tx tsu interface
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output tx_q_rst_out,
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output tx_q_rst_out,
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output tx_q_rd_clk_out,
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output tx_q_rd_clk_out,
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output tx_q_rd_en_out,
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output tx_q_rd_en_out,
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output [ 7:0] tx_q_ptp_msgid_mask_out,
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input [ 7:0] tx_q_stat_in,
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input [ 7:0] tx_q_stat_in,
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input [127:0] tx_q_data_in
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input [127:0] tx_q_data_in
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);
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);
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parameter const_00 = 8'h00;
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parameter const_00 = 8'h00;
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| Line 264... |
Line 266... |
//wire = reg_40[ 4];
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//wire = reg_40[ 4];
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//wire = reg_40[ 3];
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//wire = reg_40[ 3];
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//wire = reg_40[ 2];
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//wire = reg_40[ 2];
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wire rxq_rst = reg_40[ 1];
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wire rxq_rst = reg_40[ 1];
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wire rxqu_rd = reg_40[ 0];
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wire rxqu_rd = reg_40[ 0];
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assign rx_q_ptp_msgid_mask_out [7:0] = reg_44[31:24];
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// register mapping: TSU TX
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// register mapping: TSU TX
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//wire = reg_60[ 7];
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//wire = reg_60[ 7];
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//wire = reg_60[ 6];
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//wire = reg_60[ 6];
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//wire = reg_60[ 5];
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//wire = reg_60[ 5];
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//wire = reg_60[ 4];
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//wire = reg_60[ 4];
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//wire = reg_60[ 3];
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//wire = reg_60[ 3];
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//wire = reg_60[ 2];
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//wire = reg_60[ 2];
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wire txq_rst = reg_60[ 1];
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wire txq_rst = reg_60[ 1];
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wire txqu_rd = reg_60[ 0];
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wire txqu_rd = reg_60[ 0];
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// TODO: add configurable PTP Event msgID value mask
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assign tx_q_ptp_msgid_mask_out [7:0] = reg_64[31:24];
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// TODO: add configurable VLANTPID values
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// TODO: add configurable VLANTPID values
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// real time clock
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// real time clock
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reg rtc_rst_s1, rtc_rst_s2, rtc_rst_s3;
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reg rtc_rst_s1, rtc_rst_s2, rtc_rst_s3;
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assign rtc_rst_out = rtc_rst_s2 && !rtc_rst_s3;
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assign rtc_rst_out = rtc_rst_s2 && !rtc_rst_s3;
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