| Line 205... |
Line 205... |
reg txqu_ok;
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reg txqu_ok;
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reg [31:0] data_out_reg;
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reg [31:0] data_out_reg;
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always @(posedge clk) begin
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always @(posedge clk) begin
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// register mapping: RTC
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// register mapping: RTC
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if (rd_in && cs_00) data_out_reg <= {reg_00[31: 2], adj_ld_done_in, time_ok};
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if (rd_in && cs_00) data_out_reg <= {27'd0, reg_00[ 4: 2], adj_ld_done_in, time_ok};
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if (rd_in && cs_04) data_out_reg <= reg_04;
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if (rd_in && cs_04) data_out_reg <= 32'd0;
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if (rd_in && cs_08) data_out_reg <= reg_08;
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if (rd_in && cs_08) data_out_reg <= 32'd0;
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if (rd_in && cs_0c) data_out_reg <= reg_0c;
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if (rd_in && cs_0c) data_out_reg <= 32'd0;
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if (rd_in && cs_10) data_out_reg <= {16'd0, time_reg_sec_int[47:32]};
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if (rd_in && cs_10) data_out_reg <= {16'd0, time_reg_sec_int[47:32]};
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if (rd_in && cs_14) data_out_reg <= time_reg_sec_int[31: 0] ;
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if (rd_in && cs_14) data_out_reg <= time_reg_sec_int[31: 0] ;
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if (rd_in && cs_18) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]};
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if (rd_in && cs_18) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]};
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if (rd_in && cs_1c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]};
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if (rd_in && cs_1c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]};
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if (rd_in && cs_20) data_out_reg <= reg_20;
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if (rd_in && cs_20) data_out_reg <= {24'd0, reg_20[ 7: 0]};
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if (rd_in && cs_24) data_out_reg <= reg_24;
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if (rd_in && cs_24) data_out_reg <= reg_24;
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if (rd_in && cs_28) data_out_reg <= reg_28;
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if (rd_in && cs_28) data_out_reg <= {24'd0, reg_28[ 7: 0]};
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if (rd_in && cs_2c) data_out_reg <= reg_2c;
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if (rd_in && cs_2c) data_out_reg <= reg_2c;
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if (rd_in && cs_30) data_out_reg <= reg_30;
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if (rd_in && cs_30) data_out_reg <= reg_30;
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if (rd_in && cs_34) data_out_reg <= reg_34;
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if (rd_in && cs_34) data_out_reg <= 32'd0;
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if (rd_in && cs_38) data_out_reg <= reg_38;
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if (rd_in && cs_38) data_out_reg <= 32'd0;
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if (rd_in && cs_3c) data_out_reg <= reg_3c;
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if (rd_in && cs_3c) data_out_reg <= 32'd0;
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// register mapping: TSU RX
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// register mapping: TSU RX
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if (rd_in && cs_40) data_out_reg <= {reg_40[31: 2], reg_40[ 1], rxqu_ok};
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if (rd_in && cs_40) data_out_reg <= {30'd0, reg_40[ 1], rxqu_ok};
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if (rd_in && cs_44) data_out_reg <= {24'd0, rx_q_stat_int[ 7: 0]};
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if (rd_in && cs_44) data_out_reg <= {reg_44[31:24], 16'd0, rx_q_stat_int[ 7: 0]};
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if (rd_in && cs_48) data_out_reg <= reg_48;
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if (rd_in && cs_48) data_out_reg <= 32'd0;
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if (rd_in && cs_4c) data_out_reg <= reg_4c;
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if (rd_in && cs_4c) data_out_reg <= 32'd0;
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if (rd_in && cs_50) data_out_reg <= rx_q_data_int[127: 96];
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if (rd_in && cs_50) data_out_reg <= rx_q_data_int[127: 96];
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if (rd_in && cs_54) data_out_reg <= rx_q_data_int[ 95: 64];
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if (rd_in && cs_54) data_out_reg <= rx_q_data_int[ 95: 64];
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if (rd_in && cs_58) data_out_reg <= rx_q_data_int[ 63: 32];
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if (rd_in && cs_58) data_out_reg <= rx_q_data_int[ 63: 32];
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if (rd_in && cs_5c) data_out_reg <= rx_q_data_int[ 31: 0];
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if (rd_in && cs_5c) data_out_reg <= rx_q_data_int[ 31: 0];
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// register mapping: TSU TX
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// register mapping: TSU TX
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if (rd_in && cs_60) data_out_reg <= {reg_60[31: 2], reg_60[ 1], txqu_ok};
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if (rd_in && cs_60) data_out_reg <= {30'd0, reg_60[ 1], txqu_ok};
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if (rd_in && cs_64) data_out_reg <= {24'd0, tx_q_stat_int[ 7: 0]};
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if (rd_in && cs_64) data_out_reg <= {reg_64[31:24], 16'd0, tx_q_stat_int[ 7: 0]};
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if (rd_in && cs_68) data_out_reg <= reg_68;
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if (rd_in && cs_68) data_out_reg <= 32'd0;
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if (rd_in && cs_6c) data_out_reg <= reg_6c;
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if (rd_in && cs_6c) data_out_reg <= 32'd0;
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if (rd_in && cs_70) data_out_reg <= tx_q_data_int[127: 96];
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if (rd_in && cs_70) data_out_reg <= tx_q_data_int[127: 96];
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if (rd_in && cs_74) data_out_reg <= tx_q_data_int[ 95: 64];
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if (rd_in && cs_74) data_out_reg <= tx_q_data_int[ 95: 64];
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if (rd_in && cs_78) data_out_reg <= tx_q_data_int[ 63: 32];
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if (rd_in && cs_78) data_out_reg <= tx_q_data_int[ 63: 32];
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if (rd_in && cs_7c) data_out_reg <= tx_q_data_int[ 31: 0];
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if (rd_in && cs_7c) data_out_reg <= tx_q_data_int[ 31: 0];
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end
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end
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