Line 123... |
Line 123... |
wire cs_74 = (addr_in[7:2]==const_74[7:2])? 1'b1: 1'b0;
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wire cs_74 = (addr_in[7:2]==const_74[7:2])? 1'b1: 1'b0;
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wire cs_78 = (addr_in[7:2]==const_78[7:2])? 1'b1: 1'b0;
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wire cs_78 = (addr_in[7:2]==const_78[7:2])? 1'b1: 1'b0;
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wire cs_7c = (addr_in[7:2]==const_7c[7:2])? 1'b1: 1'b0;
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wire cs_7c = (addr_in[7:2]==const_7c[7:2])? 1'b1: 1'b0;
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reg [31:0] reg_00; // ctrl 5 bit
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reg [31:0] reg_00; // ctrl 5 bit
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reg [31:0] reg_04; // null
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reg [31:0] reg_04; // scratch reg
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reg [31:0] reg_08; // null
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reg [31:0] reg_08; // null
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reg [31:0] reg_0c; // null
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reg [31:0] reg_0c; // null
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reg [31:0] reg_10; // time 16 bit s
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reg [31:0] reg_10; // time 16 bit s
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reg [31:0] reg_14; // time 32 bit s
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reg [31:0] reg_14; // time 32 bit s
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reg [31:0] reg_18; // time 30 bit ns
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reg [31:0] reg_18; // time 30 bit ns
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Line 206... |
Line 206... |
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reg [31:0] data_out_reg;
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reg [31:0] data_out_reg;
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always @(posedge clk) begin
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always @(posedge clk) begin
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// register mapping: RTC
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// register mapping: RTC
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if (rd_in && cs_00) data_out_reg <= {27'd0, reg_00[ 4: 2], adj_ld_done_in, time_ok};
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if (rd_in && cs_00) data_out_reg <= {27'd0, reg_00[ 4: 2], adj_ld_done_in, time_ok};
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if (rd_in && cs_04) data_out_reg <= 32'd0;
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if (rd_in && cs_04) data_out_reg <= reg_04;
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if (rd_in && cs_08) data_out_reg <= 32'd0;
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if (rd_in && cs_08) data_out_reg <= 32'd0;
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if (rd_in && cs_0c) data_out_reg <= 32'd0;
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if (rd_in && cs_0c) data_out_reg <= 32'd0;
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if (rd_in && cs_10) data_out_reg <= {16'd0, time_reg_sec_int[47:32]};
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if (rd_in && cs_10) data_out_reg <= {16'd0, time_reg_sec_int[47:32]};
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if (rd_in && cs_14) data_out_reg <= time_reg_sec_int[31: 0] ;
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if (rd_in && cs_14) data_out_reg <= time_reg_sec_int[31: 0] ;
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if (rd_in && cs_18) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]};
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if (rd_in && cs_18) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]};
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