| Line 48... |
Line 48... |
else
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else
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time_adj <= period_fix + 0;
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time_adj <= period_fix + 0;
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end
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end
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end
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end
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wire [39:0] time_adj_08n_32f; // 39:32 ns, 31:0 ns_fraction
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reg [39:0] time_adj_08n_32f; // 39:32 ns, 31:0 ns_fraction
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wire [15:0] time_adj_08n_08f; // 15: 8 ns, 7:0 ns_fraction
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wire [15:0] time_adj_08n_08f; // 15: 8 ns, 7:0 ns_fraction
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reg [23:0] time_adj_00n_24f; // 23:0 ns_fraction
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reg [23:0] time_adj_00n_24f; // 23:0 ns_fraction
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// delta-sigma circuit to keep the lower 24bit of time_adj
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// delta-sigma circuit to keep the lower 24bit of time_adj
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assign time_adj_08n_32f = time_adj[39: 0] + {16'd0, time_adj_00n_24f}; // sigma the delta part
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always @(posedge rst or posedge clk) begin
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always @(posedge rst or posedge clk) begin // keep the delta part
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if (rst) begin
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if (rst) begin
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time_adj_08n_32f <= 40'd0;
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time_adj_00n_24f <= 24'd0;
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time_adj_00n_24f <= 24'd0;
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end
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end
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else begin
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else begin
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time_adj_00n_24f <= time_adj_08n_32f[23: 0];
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time_adj_08n_32f <= time_adj[39: 0] + {16'd0, time_adj_00n_24f}; // add the delta
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time_adj_00n_24f <= time_adj_08n_32f[23: 0]; // save the delta
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end
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end
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end
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end
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assign time_adj_08n_08f = time_adj_08n_32f[39:24]; // output w/o the delta part
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assign time_adj_08n_08f = time_adj_08n_32f[39:24]; // output w/o the delta
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reg [37:0] time_acc_30n_08f; // 37:8 ns , 7:0 ns_fraction
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reg [37:0] time_acc_30n_08f; // 37:8 ns , 7:0 ns_fraction
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reg [47:0] time_acc_48s; // 47:0 sec
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reg [47:0] time_acc_48s; // 47:0 sec
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reg time_acc_48s_inc;
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// time accumulator (48bit_s + 30bit_ns + 8bit_ns_fraction)
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// time accumulator (48bit_s + 30bit_ns + 8bit_ns_fraction)
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always @(posedge rst or posedge clk) begin
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always @(posedge rst or posedge clk) begin
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if (rst) begin
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if (rst) begin
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time_acc_30n_08f <= 38'd0;
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time_acc_30n_08f <= 38'd0;
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time_acc_48s <= 48'd0;
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time_acc_48s <= 48'd0;
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time_acc_48s_inc <= 1'b0;
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end
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end
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else begin
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else begin
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if (time_ld) begin // direct write
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if (time_ld) begin // direct write
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time_acc_30n_08f <= time_reg_ns_in;
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time_acc_30n_08f <= time_reg_ns_in;
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time_acc_48s <= time_reg_sec_in;
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time_acc_48s <= time_reg_sec_in;
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end
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end
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else if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} >= time_acc_modulo) begin
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time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f} - time_acc_modulo;
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time_acc_48s <= time_acc_48s + 1;
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end
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else begin
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else begin
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|
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if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} >= time_acc_modulo)
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time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f} - time_acc_modulo;
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else
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time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f};
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time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f};
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|
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if (time_acc_48s_inc)
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time_acc_48s_inc <= 1'b0;
|
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else if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} + {22'd0, time_adj_08n_08f} >= time_acc_modulo)
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time_acc_48s_inc <= 1'b1;
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else
|
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time_acc_48s_inc <= 1'b0;
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|
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if (time_acc_48s_inc)
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time_acc_48s <= time_acc_48s + 1;
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else
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time_acc_48s <= time_acc_48s;
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time_acc_48s <= time_acc_48s;
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|
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end
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end
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end
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end
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end
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end
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// time output (48bit_s + 30bit_ns + 8bit_ns_fraction)
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// time output (48bit_s + 30bit_ns + 8bit_ns_fraction)
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