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[/] [ha1588/] [trunk/] [rtl/] [rtc/] [rtc.v] - Diff between revs 19 and 22

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Rev 19 Rev 22
Line 24... Line 24...
reg  [31:0] adj_cnt;
reg  [31:0] adj_cnt;
reg  [39:0] time_adj;    // 39:32 ns, 31:0 ns_fraction
reg  [39:0] time_adj;    // 39:32 ns, 31:0 ns_fraction
// frequency and small time difference adjustment registers
// frequency and small time difference adjustment registers
always @(posedge rst or posedge clk) begin
always @(posedge rst or posedge clk) begin
  if (rst) begin
  if (rst) begin
    period_fix <= 40'd0;
    period_fix <= period_fix;  //40'd0;
    adj_cnt    <= 32'hffffffff;
    adj_cnt    <= 32'hffffffff;
    time_adj   <= 40'd0;
    time_adj   <= time_adj;    //40'd0;
  end
  end
  else begin
  else begin
    if (period_ld)  // load period adjustment
    if (period_ld)  // load period adjustment
      period_fix <= period_in;
      period_fix <= period_in;
    else
    else
Line 88... Line 88...
      else
      else
        time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f};
        time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f};
 
 
      if (time_acc_48s_inc)
      if (time_acc_48s_inc)
        time_acc_48s_inc <= 1'b0;
        time_acc_48s_inc <= 1'b0;
 
      else if (time_acc_modulo == 38'd0)
 
        time_acc_48s_inc <= 1'b0;
      else if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} + {22'd0, time_adj_08n_08f} >= time_acc_modulo)
      else if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} + {22'd0, time_adj_08n_08f} >= time_acc_modulo)
        time_acc_48s_inc <= 1'b1;
        time_acc_48s_inc <= 1'b1;
      else
      else
        time_acc_48s_inc <= 1'b0;
        time_acc_48s_inc <= 1'b0;
 
 

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