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https://opencores.org/ocsvn/ha1588/ha1588/trunk
[/] [ha1588/] [trunk/] [rtl/] [rtc/] [rtc.v] - Diff between revs 19 and 22
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Rev 19 |
Rev 22 |
Line 24... |
Line 24... |
reg [31:0] adj_cnt;
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reg [31:0] adj_cnt;
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reg [39:0] time_adj; // 39:32 ns, 31:0 ns_fraction
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reg [39:0] time_adj; // 39:32 ns, 31:0 ns_fraction
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// frequency and small time difference adjustment registers
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// frequency and small time difference adjustment registers
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always @(posedge rst or posedge clk) begin
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always @(posedge rst or posedge clk) begin
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if (rst) begin
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if (rst) begin
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period_fix <= 40'd0;
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period_fix <= period_fix; //40'd0;
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adj_cnt <= 32'hffffffff;
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adj_cnt <= 32'hffffffff;
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time_adj <= 40'd0;
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time_adj <= time_adj; //40'd0;
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end
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end
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else begin
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else begin
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if (period_ld) // load period adjustment
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if (period_ld) // load period adjustment
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period_fix <= period_in;
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period_fix <= period_in;
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else
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else
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Line 88... |
Line 88... |
else
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else
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time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f};
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time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f};
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if (time_acc_48s_inc)
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if (time_acc_48s_inc)
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time_acc_48s_inc <= 1'b0;
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time_acc_48s_inc <= 1'b0;
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else if (time_acc_modulo == 38'd0)
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time_acc_48s_inc <= 1'b0;
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else if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} + {22'd0, time_adj_08n_08f} >= time_acc_modulo)
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else if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} + {22'd0, time_adj_08n_08f} >= time_acc_modulo)
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time_acc_48s_inc <= 1'b1;
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time_acc_48s_inc <= 1'b1;
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else
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else
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time_acc_48s_inc <= 1'b0;
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time_acc_48s_inc <= 1'b0;
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