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/*
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/*
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* $rtc.v
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* rtc.v
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*
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*
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* Copyright (c) 2012, BABY&HW. All rights reserved.
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* Copyright (c) 2012, BABY&HW. All rights reserved.
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*
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*
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* This library is free software; you can redistribute it and/or
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* modify it under the terms of the GNU Lesser General Public
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input [37:0] time_reg_ns_in, // 37:8 ns, 7:0 ns_fraction
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input [37:0] time_reg_ns_in, // 37:8 ns, 7:0 ns_fraction
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input [47:0] time_reg_sec_in, // 47:0 sec
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input [47:0] time_reg_sec_in, // 47:0 sec
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// 2. frequency adjustment: frequency set up for drift compensation
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// 2. frequency adjustment: frequency set up for drift compensation
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input period_ld,
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input period_ld,
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input [39:0] period_in, // 39:32 ns, 31:0 ns_fraction
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input [39:0] period_in, // 39:32 ns, 31:0 ns_fraction
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input [37:0] time_acc_modulo, // 37: 8 ns, 7:0 ns_fraction
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// 3. precise time adjustment: small time difference adjustment with a time mark
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// 3. precise time adjustment: small time difference adjustment with a time mark
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input adj_ld,
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input adj_ld,
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input [31:0] adj_ld_data,
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input [31:0] adj_ld_data,
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output reg adj_ld_done,
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input [39:0] period_adj, // 39:32 ns, 31:0 ns_fraction
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input [39:0] period_adj, // 39:32 ns, 31:0 ns_fraction
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// time output: for internal with ns fraction
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// time output: for internal with ns fraction
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output [37:0] time_reg_ns, // 37:8 ns, 7:0 ns_fraction
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output [37:0] time_reg_ns, // 37:8 ns, 7:0 ns_fraction
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output [47:0] time_reg_sec, // 47:0 sec
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output [47:0] time_reg_sec, // 47:0 sec
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// time output: for external with ptp standard
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// time output: for external with ptp standard
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output [31:0] time_ptp_ns, // 31:0 ns
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output [31:0] time_ptp_ns, // 31:0 ns
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output [47:0] time_ptp_sec // 47:0 sec
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output [47:0] time_ptp_sec // 47:0 sec
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);
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);
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parameter time_acc_modulo = 38'd256000000000;
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reg [39:0] period_fix; // 39:32 ns, 31:0 ns_fraction
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reg [39:0] period_fix; // 39:32 ns, 31:0 ns_fraction
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reg [31:0] adj_cnt;
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reg [31:0] adj_cnt;
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reg [39:0] time_adj; // 39:32 ns, 31:0 ns_fraction
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reg [39:0] time_adj; // 39:32 ns, 31:0 ns_fraction
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// frequency and small time difference adjustment registers
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// frequency and small time difference adjustment registers
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always @(posedge rst or posedge clk) begin
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always @(posedge rst or posedge clk) begin
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if (rst) begin
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if (rst) begin
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period_fix <= period_fix; //40'd0;
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period_fix <= period_fix; //40'd0;
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adj_cnt <= 32'hffffffff;
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adj_cnt <= 32'hffffffff;
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time_adj <= time_adj; //40'd0;
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time_adj <= time_adj; //40'd0;
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adj_ld_done <= 1'b0;
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end
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end
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else begin
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else begin
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if (period_ld) // load period adjustment
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if (period_ld) // load period adjustment
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period_fix <= period_in;
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period_fix <= period_in;
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else
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else
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if (adj_cnt==0) // change period temparorily
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if (adj_cnt==0) // change period temparorily
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time_adj <= period_fix + period_adj;
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time_adj <= period_fix + period_adj;
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else
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else
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time_adj <= period_fix + 0;
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time_adj <= period_fix + 0;
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if (adj_cnt==32'hffffffff)
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adj_ld_done <= 1'b1;
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else
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adj_ld_done <= 1'b0;
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end
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end
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end
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end
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reg [39:0] time_adj_08n_32f; // 39:32 ns, 31:0 ns_fraction
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reg [39:0] time_adj_08n_32f; // 39:32 ns, 31:0 ns_fraction
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wire [15:0] time_adj_08n_08f; // 15: 8 ns, 7:0 ns_fraction
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wire [15:0] time_adj_08n_08f; // 15: 8 ns, 7:0 ns_fraction
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else
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else
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time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f};
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time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f};
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if (time_acc_48s_inc)
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if (time_acc_48s_inc)
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time_acc_48s_inc <= 1'b0;
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time_acc_48s_inc <= 1'b0;
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else if (time_acc_modulo == 38'd0)
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else if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} + {22'd0, time_adj_08n_08f} >= time_acc_modulo) // TODO: period_adj
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time_acc_48s_inc <= 1'b0;
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else if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} + {22'd0, time_adj_08n_08f} >= time_acc_modulo)
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time_acc_48s_inc <= 1'b1;
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time_acc_48s_inc <= 1'b1;
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else
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else
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time_acc_48s_inc <= 1'b0;
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time_acc_48s_inc <= 1'b0;
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if (time_acc_48s_inc)
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if (time_acc_48s_inc)
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